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Noiseshaped D/A-Converters

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High-Performance D/A-Converters

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 36))

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Abstract

As described in Sect. 2.3.1, noiseshaping can be used in oversampled data converters to trade off bandwidth with resolution. In a \(\Sigma \Delta \)-DAC a digital noiseshaper preprocesses the input data before the actual conversion to the analog domain. Because the D/A-conversion happens outside of the noise-shaping loop, any nonideality related to this conversion is directly injected into the analog output.

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Notes

  1. 1.

    From a system perspective, this is also true for the feedback DAC in a \(\Sigma \Delta \)-ADC. In both cases the conversion from digital to analog takes place outside of the noise-shaping loop and thus is likely to determine the performance of the converter.

  2. 2.

    In DSL-systems clock rates and signal bandwidths are multiples of the 4.3125 kHz symbol rate.

  3. 3.

    The matching constants are derived from closely spaced devices with perfect common-centroid layout to exclude long distance effects like processing gradients. It is not possible to maintain such a degree of matching in an extended current-source array, unless a complex matrix-based switching scheme is employed [64].

  4. 4.

    As is evident from Fig. 5.5, in terms of silicon area, the cascode transistors are practically negligible in comparison to the current-source transistors.

  5. 5.

    A rise-fall time mismatch of 200 ps would be sufficient to generate the measured HD2.

  6. 6.

    Again, we desire to have a design margin of about 1 bit.

  7. 7.

    The functions synthesizeNTF.m, simulateSNR.m, clans.m, and realizeNTF.m are used to find a stable NTF with optimized in-band SNR.

  8. 8.

    CLA is most effective with P = 1, because then any static input code c uses all elements of the array in one revolution of the index pointer. With N = 64, P = 32, any static input code c ≤ P uses only 2c elements.

References

  1. S. Wimoesterer, VDSL2. Funkschau, Heft 17/2005 (2005), pp. 43–44

    Google Scholar 

  2. R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters (Wiley, Hoboken, New Jersey, 2004). ISBN:0-471-46585-2

    Google Scholar 

  3. R. Adams, K.Q. Nguyen, K. Sweetland, A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling. IEEE J. Solid-State Circ. 33(12), 1871–1878 (1998)

    Article  Google Scholar 

  4. G. Van Der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, G. Gielen, A 14-bit intrinsic accuracy Q 2 random walk CMOS DAC. IEEE J. Solid-State Circ. 34(12), 1708–1718 (1999)

    Article  Google Scholar 

  5. R. Baird, T. Fiez, Improved \(\Delta \Sigma \) DAC linearity using data weighted averaging, in Proceedings of the 1995 International Symposium on Circuits and Systems, vol. 1, pp. I–13 – I–16, 1995

    Google Scholar 

  6. M. Clara, A. Wiesbauer, W. Klatzer, Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors, in Proceedings of the 2004 International Symposium on Circuits and Systems, vol. 1, pp. I–285 – I–288, 2004

    Google Scholar 

  7. X.-M. Gong, E. Gaalaas, M. Alexander, D. Hester, E. Walburger, J. Bian, A 120 dB multi-bit SC audio DAC with second-order noise shaping. IEEE International Solid-State Circuits Conference 2000, Digest of Technical Papers, pp. 344–345, 2000

    Google Scholar 

  8. P. Pessl, R. Gaggl, J. Hohl, D. Giotta, J. Hauptmann, A four-channel ADSL2+ analog front-end for CO applications with 75 mW per channel, built in 0. 13μm CMOS. IEEE J. Solid-State Circ. 39(12), 2371–2378 (2004)

    Google Scholar 

  9. K. Falakshahi, C.-K. Yang, B. Wooley, A 14-bit, 10-Msamples/s D/A converter using multi-bit \(\Sigma \Delta \) modulation. IEEE J. Solid-State Circ. 34(5), 607–615 (1999)

    Article  Google Scholar 

  10. A. Van den Bosch, M. Steyaert, W. Sansen, A 10-bit 1-GSample/s nyquist current-steering CMOS D/A converter. IEEE J. Solid-State Circ. 36(3), 315–324 (2001)

    Article  Google Scholar 

  11. M. Clara, W. Klatzer, A. Wiesbauer, D. Straeussnigg, A 350MHz low-OSR \(\Sigma \Delta \) current-steering DAC with active termination in 0. 13μm CMOS. IEEE International Solid-State Circuits Conference 2005, Digest of Technical Papers, pp. 118–119, 2005

    Google Scholar 

  12. R. Khoini-Poorfard, L.B. Lim, D.A. Johns, Time-interleaved oversampling A/D converters: theory and practice. IEEE Trans. Circ. Syst. II: Analog Digital Signal Process. 44(8), 634–645 (1997)

    Article  Google Scholar 

  13. D. Giotta, P. Pessl, M. Clara, W. Klatzer, R. Gaggl, Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0. 13μm CMOS, in Proceedings of the 30th European Solid-State Circuits Conference, pp. 163–166, 2004

    Google Scholar 

  14. J. Kenney, F. Sabouri, V. Leung, J. Guido, E. Zimany, A. Agrillo, J. Trackim, J. Khoury, R. Shariatdoust, A 4 channel analog front end for central office ADSL modems, in Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, pp. 307–310, 2000

    Google Scholar 

  15. S. Lin, D. Li, W. Chen, 1 V 1.25 GS/s 8 mW D/A converters for MB-OFDM UWB transceivers. IEEE International Conference on Ultra-Wideband, ICUWB, 2007, pp. 453–456, 2007

    Google Scholar 

  16. C. Sandner, M. Clara, A. Santner, T. Hartig, F. Kuttner, A 6-bit 1.2-GS/s low-power flash-ADC in 0. 13μm digital CMOS. IEEE J. Solid-State Circ. 40(7), 1499–1505 (2005)

    Google Scholar 

  17. L. Wadhwa, Simulation of third-order systems with double-lead using one operational amplifier. Proc. IRE. 50(6), 1538–1539 (1962)

    Google Scholar 

  18. Analog Devices Inc., AD8057: Low cost, single, high performance voltage feedback, 325 MHz amplifier. Datasheet (2003), http://www.analog.com/

  19. R. Schreier, Noise-shaped coding, Ph.D. dissertation, University of Toronto, 1991

    Google Scholar 

  20. R. Schreier, Delta-Sigma Toolbox, MATLABTM toolbox (2000), http://www.mathworks.com/matlabcentral/fileexchange

  21. M. Clara, W. Klatzer, A. Wiesbauer, Method for digital/analog conversion and corresponding digital/analog converter device, U.S. Patent 7,199,741, 3 Apr 2007

    Google Scholar 

  22. S. Rabii, B. Wooley, A 1.8-V digital-audio sigma-delta modulator in 0. 8μm CMOS. IEEE J. Solid-State Circ. 32(6), 1026–1034 (1997)

    Google Scholar 

  23. P. Kinget, M. Steyaert, Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits, in Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, pp. 333–336, 1996

    Google Scholar 

  24. K. Uyttenhove, M. Steyaert, Speed-power-accuracy trade-off in high-speed CMOS ADC’s. IEEE Trans. Circuits Syst. II. 49(4), 280–287 (2002)

    Article  Google Scholar 

  25. H. Schouwenaars, W. Groeneveld, C. Bastiaansen, H. Termeer, An oversampled multibit CMOS D/A converter for digital audio with 115-dB dynamic range. IEEE J. Solid-State Circ. 26(12), 1775–1780 (1991)

    Article  Google Scholar 

  26. D.K. Su, B. Wooley, A CMOS oversampling D/A converter with a current-mode semidigital reconstruction filter. IEEE J. Solid-State Circ. 28(12), 1224–1233 (1993)

    Article  Google Scholar 

  27. T. Hamasaki, Y. Shinohara, H. Terasawa, K.-I. Ochiai, M. Hiraoka, H. Kanayama, A 3-V, 22-mW multibit current-mode \(\Sigma \Delta \) DAC with 100 dB dynamic range. IEEE Journal of Solid-State Circ. 31(12), 1888–1894 (1996)

    Article  Google Scholar 

  28. I. Fujimori, A. Nogi, T. Sugimoto, A multibit delta-sigma audio DAC with 120-dB dynamic range. IEEE J. Solid-State Circ. 35(8), 1066–1073 (2000)

    Article  Google Scholar 

  29. M. Annovazzi, V. Colonna, G. Gandolfi, F. Stefani, A. Baschirotto, A Low-Power 98-dB multibit audio DAC in a standard 3.3-V 0. 35μm CMOS technology. IEEE J. Solid-State Circ. 37(7), 825–834 (2002)

    Google Scholar 

  30. T. Rueger, B. Duewer, S. Hodapp, T. Lei, J. Melanson, B. Trotter, A 110dB ternary PWM current-mode audio DAC with monolithic 2Vrms driver. IEEE International Solid-State Circuits Conference 2004, Digest of Technical Papers, 372–373, 2004

    Google Scholar 

  31. P. Francese, P. Ferrat, Q. Huang, A 13-b 1.1-MHz Oversampled DAC with semidigital reconstruction filtering. IEEE J. Solid-State Circ. 39(12), 2098–2106 (2004)

    Google Scholar 

  32. K. Nguyen, A. Bandyopadhyay, B. Adams, K. Sweetland, P. Baginski, A 108 dB SNR, 1.1mW oversampling audio DAC with a three-level DEM technique. IEEE J. Solid-State Circ. 43(12), 2592–2600 (2008)

    Google Scholar 

  33. V. Colonna, M. Annovazzi, G. Boarin, G. Gandolfi, F. Stefani, A. Baschirotto, A 0.22-mm 2 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNR OUT . IEEE J. Solid-State Circ. 40(7), 1491–1498 (2005)

    Google Scholar 

  34. Y.-H. Lee, M.-Y. Choi, S.-B. You, W.-S. Yeum, H.-J. Park, J.-W. Kim, A 4mW per-Channel 101dB-DR stereo audio DAC with transformed quantization structure, in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, pp. 145–148, 2006

    Google Scholar 

  35. L. Risbo, R. Hezar, B. Kelleci, H. Kiper, M. Fares, A 108dB-DR 120dB-THD and 0.5Vrms output audio DAC with Inter-symbol-interference-shaping algorithm in 45nm CMOS. IEEE International Solid-State Circuits Conference 2005, Digest of Technical Papers, pp. 484–485, 2011

    Google Scholar 

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  1. LANTIQ-A GmbH, Villach, Austria

    Martin Clara

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Clara, M. (2013). Noiseshaped D/A-Converters. In: High-Performance D/A-Converters. Springer Series in Advanced Microelectronics, vol 36. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31229-8_5

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  • DOI: https://doi.org/10.1007/978-3-642-31229-8_5

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