Abstract
A major challenge in hardware verification is managing the state explosion problem in pre-silicon verification. This is seen in the high cost and low coverage of simulation, and capacity limitations of formal verification. Runtime verification, through on-the-fly property checking of the current trace and a low-cost error recovery mechanism, provides us an alternative attack in dealing with this problem. There are several interesting examples of runtime verification that have been proposed in recent years in the computer architecture community. These have also been motivated by the resiliency needs of future technology generations in the face of dynamic errors due to device failures. I will first highlight the key ideas in hardware runtime verification through specific examples from the uni-processor and multi-processor contexts. Next, I will discuss the challenges in implementing some of these solutions. Finally I will discuss how the strengths of runtime verification and model checking can be used in a complementary fashion for hardware.
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References
Austin, T.M., Bertacco, V., Blaauw, D., Mudge, T.N.: Opportunities and challenges for better than worst-case design. In: Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 2–7. ACM (2005)
Austin, T.M.: DIVA: a reliable substrate for deep submicron microarchitecture design. In: ACM/IEEE International Symposium on Microarchitecture (MICRO), pp. 196–207. IEEE Computer Society (1999)
Wagner, I., Bertacco, V.: Engineering trust with semantic guardians. In: Design Automation and Test in Europe (DATE), EDA Consortium, pp. 743–748 (2007)
Adve, S.V., Gharachorloo, K.: Shared memory consistency models: A tutorial. IEEE Computer 29, 66–76 (1996)
Cain, H.W., Lipasti, M.H., Nair, R.: Constraint graph analysis of multithreaded programs. Journal of Instruction-Level Parallelism 6 (2004)
Chen, K., Malik, S., Patra, P.: Runtime validation of memory ordering using constraint graph checking. In: International Conference on High-Performance Computer Architecture (HPCA), pp. 415–426. IEEE Computer Society (2008)
Chen, K., Malik, S., Patra, P.: Runtime validation of transactional memory systems. In: International Symposium on Quality of Electronic Design (ISQED), pp. 750–756. IEEE Computer Society (2008)
Meixner, A., Sorin, D.J.: Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures. IEEE Transactions on Dependable Secure Computing 6, 18–31 (2009)
Prvulovic, M., Torrellas, J., Zhang, Z.: ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors. In: International Symposium on Computer Architecture (ISCA), pp. 111–122. IEEE Computer Society (2002)
Sorin, D.J., Martin, M.M.K., Hill, M.D., Wood, D.A.: SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery. In: International Symposium on Computer Architecture (ISCA), pp. 123–134. IEEE Computer Society (2002)
Sarangi, S.R., Tiwari, A., Torrellas, J.: Phoenix: Detecting and recovering from permanent processor design bugs with programmable hardware. In: ACM/IEEE International Symposium on Microarchitecture (MICRO), pp. 26–37. IEEE Computer Society (2006)
Wagner, I., Bertacco, V., Austin, T.M.: Shielding against design flaws with field repairable control logic. In: Design Automation Conference (DAC), pp. 344–347. ACM (2006)
Abarbanel, Y., Beer, I., Gluhovsky, L., Keidar, S., Wolfsthal, Y.: FoCs: Automatic Generation of Simulation Checkers from Formal Specifications. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855, pp. 538–542. Springer, Heidelberg (2000)
Bayazit, A.A., Malik, S.: Complementary use of runtime validation and model checking. In: International Conference on Computer-Aided Design (ICCAD), pp. 1052–1059. IEEE Computer Society (2005)
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Malik, S. (2012). Runtime Verification: A Computer Architecture Perspective. In: Khurshid, S., Sen, K. (eds) Runtime Verification. RV 2011. Lecture Notes in Computer Science, vol 7186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29860-8_5
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DOI: https://doi.org/10.1007/978-3-642-29860-8_5
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