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Designing Feedback Latches

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Logic Circuit Design

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Abstract

The memory evaluation-formulas of the previous chapter are the backbone to designing feedback latches (such as the relay circuit of Fig. 9.1b). Yet, feedback can only be realised if we can show that the prior output Y (λ − 1) may always (i.e., for all input events) be chosen to equal the present output Y (λ)—for then and only then can we connect the two leads, thus realising feedback.

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  1. Bärenkogelweg 21, 2371, Hinterbrühl, Austria

    Shimon P. Vingron

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  1. Shimon P. Vingron
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Vingron, S.P. (2012). Designing Feedback Latches. In: Logic Circuit Design. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27657-6_10

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  • DOI: https://doi.org/10.1007/978-3-642-27657-6_10

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