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Assessing System Vulnerability Using Formal Verification Techniques

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Mathematical and Engineering Methods in Computer Science (MEMICS 2011)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 7119))

Abstract

Hardware systems are becoming more and more vulnerable to soft errors caused by radiation or process variations. Design techniques to cope with these problems are built into the system. But how to verify that the final system is as resilient as expected? The paper covers modeling issues related to assessing fault tolerance and reliability. Existing approaches are reviewed that analyze transient faults on the electrical as well as the logical level. Trade-offs regarding resource requirements and quality of results are discussed and the individual advantages are highlighted.

This work has been supported in part by the German Research Foundation (DFG, grant no. 797/6-1).

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References

  1. Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. Computer Science Press (1990)

    Google Scholar 

  2. Baarir, S., Braunstein, C., Clavel, R., Encrenaz, E., Ilie, J.-M., Leveugle, R., Mounier, I., Pierre, L., Poitrenaud, D.: Complementary formal approaches for dependability analysis. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 331–339 (2009)

    Google Scholar 

  3. Biere, A., Cimatti, A., Clarke, E., Zhu, Y.: Symbolic Model Checking Without Bdds. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, pp. 193–207. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  4. Bloem, R., Chatterjee, K., Greimel, K., Henzinger, T.A., Jobstmann, B.: Robustness in the Presence of Liveness. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 410–424. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  5. Bozzano, M., Cimatti, A., Tapparo, F.: Symbolic Fault Tree Analysis For Reactive Systems. In: Namjoshi, K.S., Yoneda, T., Higashino, T., Okamura, Y. (eds.) ATVA 2007. LNCS, vol. 4762, pp. 162–176. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  6. Choudhury, M.R., Mohanram, K.: Reliability analysis of logic circuits. IEEE Trans. on CAD 28(3), 392–405 (2009)

    Article  Google Scholar 

  7. Civera, P., Macchiarulo, L., Rebaudengo, M., Sonza Reorda, M., Violante, M.: An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits. Jour. of Electronic Testing: Theory and Applications 18(3), 261–271 (2002)

    Article  MATH  Google Scholar 

  8. Fey, G., Drechsler, R.: A basis for formal robustness checking. In: Int’l Symp. on Quality Electronic Design, pp. 784–789 (2008)

    Google Scholar 

  9. Frehse, S., Fey, G., Drechsler, R.: A better-than-worst-case robustness measure. In: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 78–83 (2010)

    Google Scholar 

  10. Fey, G., Sülflow, A., Frehse, S., Drechsler, R.: Effective robustness analysis using bounded model checking techniques. IEEE Trans. on CAD 30(8), 1239–1252 (2011)

    Article  Google Scholar 

  11. Gössel, M., Ocheretny, V., Sogomonyan, E., Marienfeld, D.: New Methods of Concurrent Checking. Frontiers in Electronic Testing, vol. 42. Springer, Heidelberg (2008)

    Google Scholar 

  12. Hamming, R.W.: Error detecting and error correcting codes. Bell System Technical Jour. 26(2), 147–160 (1950)

    Article  MathSciNet  Google Scholar 

  13. Hunger, M., Hellebrand, S.: Verification and analysis of self-checking properties through ATPG. In: IEEE International On-Line Testing Symposium, pp. 25–30 (2008)

    Google Scholar 

  14. Hunger, M., Hellebrand, S., Czutro, A., Polian, I., Becker, B.: ATPG-Based grading of strong fault-secureness. In: IEEE International On-Line Testing Symposium (2009)

    Google Scholar 

  15. Hayes, J.P., Polian, I., Becker, B.: An analysis framework for transient-error tolerance. In: VLSI Test Symp., pp. 249–255 (2007)

    Google Scholar 

  16. Koren, I., Krishna, C.M.: Fault-Tolerant Systems. Morgan Kaufmann (2007)

    Google Scholar 

  17. Krautz, U., Pflanz, M., Jacobi, C., Tast, H.W., Weber, K., Vierhaus, H.T.: Evaluating coverage of error detection logic for soft errors using formal methods. In: Design, Automation and Test in Europe, pp. 176–181 (2006)

    Google Scholar 

  18. Krishnaswamy, S., Plaza, S., Markov, I.L., Hayes, J.P.: Signature-based SER analysis and design of logic circuits. IEEE Trans. on CAD 28(1), 74–86 (2009)

    Article  Google Scholar 

  19. Kubo, H.: A procedure for generating test sequences to detect sequential circuit failures. NEC Res. and Dev. 12(3), 69–78 (1968)

    Google Scholar 

  20. Leveugle, R.: A new approach for early dependability evaluation based on formal property checking and controlled mutations. In: IEEE International On-Line Testing Symposium, pp. 260–265 (2005)

    Google Scholar 

  21. Miskov-Zivanov, M., Marculescu, D.: Circuit reliability analysis using symbolic techniques. IEEE Trans. on CAD 25(12), 2638–2649 (2006)

    Article  Google Scholar 

  22. Miskov-Zivanov, N., Marculescu, D.: Multiple transient faults in combinational and sequential circuits: A systematic approach. IEEE Trans. on CAD 29(10), 1614–1627 (2010)

    Article  Google Scholar 

  23. Pellegrini, A., Constantinides, K., Zhang, D., Sudhakar, S., Bertacco, V., Austin, T.: CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. In: Int’l Conf. on Comp. Design (2008)

    Google Scholar 

  24. Putzolu, G.R., Roth, J.P.: A heuristic algorithm for the testing of asynchronous circuits. IEEE Trans. on Comp., pp. 639–647 (1971)

    Google Scholar 

  25. Seshia, S.A., Li, W., Mitra, S.: Verification-guided soft error resilience. In: Design, Automation and Test in Europe, pp. 1442–1447 (2007)

    Google Scholar 

  26. Thompto, B.W., Hoppe, B.: Verification for fault tolerance of the ibm system z microprocessor. In: Design Automation Conf., pp. 525–530 (2010)

    Google Scholar 

  27. Zhao, C., Bai, X., Dey, S.: Evaluating transient error effects in digital nanometer circuits. IEEE Transactions on Reliability 56(3), 381–391 (2007)

    Article  Google Scholar 

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Fey, G. (2012). Assessing System Vulnerability Using Formal Verification Techniques. In: Kotásek, Z., Bouda, J., Černá, I., Sekanina, L., Vojnar, T., Antoš, D. (eds) Mathematical and Engineering Methods in Computer Science. MEMICS 2011. Lecture Notes in Computer Science, vol 7119. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25929-6_4

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  • DOI: https://doi.org/10.1007/978-3-642-25929-6_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-25928-9

  • Online ISBN: 978-3-642-25929-6

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