Abstract
Hardware systems are becoming more and more vulnerable to soft errors caused by radiation or process variations. Design techniques to cope with these problems are built into the system. But how to verify that the final system is as resilient as expected? The paper covers modeling issues related to assessing fault tolerance and reliability. Existing approaches are reviewed that analyze transient faults on the electrical as well as the logical level. Trade-offs regarding resource requirements and quality of results are discussed and the individual advantages are highlighted.
This work has been supported in part by the German Research Foundation (DFG, grant no. 797/6-1).
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Fey, G. (2012). Assessing System Vulnerability Using Formal Verification Techniques. In: Kotásek, Z., Bouda, J., Černá, I., Sekanina, L., Vojnar, T., Antoš, D. (eds) Mathematical and Engineering Methods in Computer Science. MEMICS 2011. Lecture Notes in Computer Science, vol 7119. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25929-6_4
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DOI: https://doi.org/10.1007/978-3-642-25929-6_4
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