Abstract
The last building block covered in the book is the Phase Locked Loop (PLL), virtually used in every integrated communication front-end. The complexity of this system is high; therefore the first section is dedicated to the basic concepts related to both PLL system architectures and basic components. The architecture of the classical phase locked loops used in RF IC designs are presented in that first section. Nevertheless, from the power consumption point of view, the decision on the architecture of the whole PLL is an important point, but the internal design of each block is also a key issue.
The three main and most challenging blocks are explained with a greater level of detail in subsequent sections: Phase Frequency Detector (PFD) is first described in section 8.2, then section 8.3 presents the design constraints related to the Voltage-Controlled Oscillator (VCO), and High Frequency Divider (HFD) is deeply analyzed in section 8.4. The two last blocks (VCO and HFD) are crucial in the whole power consumption of this complex circuit as these have to work in the high frequency bands of the application. Design examples are shown for these two blocks in section 8.5.
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Alvarado, U., Bistué, G., Adín, I. (2011). Phase Locked Loop (PLL) Design. In: Low Power RF Circuit Design in Standard CMOS Technology. Lecture Notes in Electrical Engineering, vol 104. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22987-9_8
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DOI: https://doi.org/10.1007/978-3-642-22987-9_8
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