Abstract
This chapter deals with the basic principles of power consumption in RF CMOS analog circuits. These concepts are used extensively throughout the book; therefore the different sections of the chapter are dedicated to the presentation of general definitions and formulas. Section 2.1 introduces the different sources of power dissipation in analogue circuits, regarding both static and dynamic power dissipation mechanisms, from a steady and transient perspective respectively. Section 2.2 reviews the classical considerations for low power digital circuits and their structures. Then, section 2.3 deals with the power supply scaling as a means to achieve low- power benefits, which is highly related to section 2.2, and finally section 2.3 outlines the practical limits in power consumption from a triple perspective: starting from the front-end architecture and CMOS technology constraints through the RF and analog circuits.
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References
Chatterjee, A., et al.: An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits. In: International Symposium on Low Power Electronics and Design, August 12-14, pp. 145–150 (1996)
Enz, C., Vittoz, E.A.: MOS Transistor Modeling for Low-Voltage and Low-Power Analog IC Design. Microelectronic Engineering 39, 59–76 (1997)
Forestier, A., Stan, M.R.: Limits to voltage scaling from the low power perspective. In: Proceedings of the 13th Symposium on Integrated Circuits and Systems Design, pp. 365–370 (2000)
Gonzalez, R., et al.: Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid-State Circuits 32(8), 1210–1216 (1997)
Hanchate, N., Ranganathan, N.: LECTOR: a technique for leakager eduction in CMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12(2), 196–205 (2004)
Yeo, K.-S., Roy, K.: Low-Voltage, Low-Power VLSI Subsystems. McGraw-Hill, New York (2005)
Lee, T.: The Design of CMOS Radio Frequency Integrated Circuits. Cambridge University Press, Cambridge (1998)
Lin, Y.-S., et al.: Leakage scaling in deep submicron CMOS for SoC. IEEE Transactions on Electron Devices 49(6), 1034–1041 (2002)
Liu, M., et al.: Scaling Limit of CMOS Supply Voltage from Noise Margin Considerations. In: 2006 International Conference on Simulation of Semiconductor Processes and Devices, September 6-8, pp. 287–289 (2006)
Menon, R.V., et al.: Switching Activity Minimization in Combinational Logic Design. In: Proceedings of the International Conference on Embedded Systems and Applications, pp. 47–53 (June 2004)
Rahman, H., Chakrabarti, C.: A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, May 23-26, vol. 2, pp. II-297–II-300 (2004)
Sun, S.-W., Tsui, P.G.Y.: Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation. IEEE Journal of Solid-State Circuits 30(8), 947–949 (1995)
Yao, L., et al.: A 0.8-V, 8-μW, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load. In: Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, September 16-18, pp. 297–300 (2003)
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Alvarado, U., Bistué, G., Adín, I. (2011). Power Considerations in Analog RF CMOS Circuits. In: Low Power RF Circuit Design in Standard CMOS Technology. Lecture Notes in Electrical Engineering, vol 104. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22987-9_2
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DOI: https://doi.org/10.1007/978-3-642-22987-9_2
Publisher Name: Springer, Berlin, Heidelberg
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