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ESL Based SoC System Bandwidth Estimation Method

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Communication Systems and Information Technology

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 100))

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Abstract

The increasing complexity of system-on-a-chip (SoC) design is challenging the design engineers to estimate the system bandwidth. A method of SoC system bandwidth estimation based on electronic-system-level (ESL) is proposed, which estimates the system bandwidth by transaction-level-modeling (TLM) and analysis depended on simulation. Compared with the traditional RTL simulation, the estimation is effective and the simulation speed is more than two orders of magnitude faster.

This work was sponsored by the National Scientific Foundation of China (Grant No. 61006029) and Jiangsu Scientific Foundation (Grant No. BK2010165)

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References

  1. Ruei-Xi, C., Wei, Z., Qinyi, L., Fan, J.: Efficient H.264 Architecture Using Modular Bandwidth Estimation. In: International Conference on Embedded Software and Systems, pp. 277–282 (2008)

    Google Scholar 

  2. Cho, Y.S., Choi, E.J., Cho, K.R.: Modeling and analysis of the system bus latency on the SoC platform. In: International Workshop on System-Level Interconnect Prediction, pp. 67–74. ACM, New York (2006)

    Chapter  Google Scholar 

  3. Zhe-Mao, H., Jen-Chieh, Y., Chuang, I.Y.: An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. In: Design, Automation & Test in Europe Conference & Exhibition, pp. 568–573 (2010)

    Google Scholar 

  4. Shin, C., Grun, P., Romdhane, N., Lennard, C., Madl, G., Pasricha, S., Dutt, N., Noll, M.: Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications. Des. Autom. Embed. Syst. 11, 119–140 (2007)

    Article  Google Scholar 

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© 2011 Springer-Verlag Berlin Heidelberg

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Xie, Z., Liu, X., Shan, W., Ge, W. (2011). ESL Based SoC System Bandwidth Estimation Method. In: Ma, M. (eds) Communication Systems and Information Technology. Lecture Notes in Electrical Engineering, vol 100. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21762-3_3

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  • DOI: https://doi.org/10.1007/978-3-642-21762-3_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-21761-6

  • Online ISBN: 978-3-642-21762-3

  • eBook Packages: EngineeringEngineering (R0)

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