Abstract
The static power of DDR PHY has increasingly become the limit of the low-power application of system-on-a-chip (SoC). An optimization of static power based on “behavior” and “state” of DDR PHY static power is proposed, considering the design principle and physical properties. Experimental results show that the proposed optimization strategy can achieve the highest 59.12% reduction in work mode and only 0.723uW power consumption in sleep mode.
This work was sponsored by the National Scientific Foundation of China (Grant No. 61006029) and Jiangsu Scientific Foundation (Grant No. BK2010165).
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© 2011 Springer-Verlag Berlin Heidelberg
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Ge, W., Zhao, M., Wu, C., He, J. (2011). The Design and Implementation of DDR PHY Static Low-Power Optimization Strategies. In: Ma, M. (eds) Communication Systems and Information Technology. Lecture Notes in Electrical Engineering, vol 100. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21762-3_1
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DOI: https://doi.org/10.1007/978-3-642-21762-3_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-21761-6
Online ISBN: 978-3-642-21762-3
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