Abstract
This paper describes a fault-tolerant scheduler that uses the Area-Time response Balancing algorithm (ATB) for scheduling real-time hardware tasks onto partially reconfigurable FPGAs. The architecture of the ATB scheduler incorporates fault-tolerance by design features; including Triple Modular Redundancy (TMR), parity protection of its memories and finite state machines, as well as spatial and implementation diversity. Additionally, it is able to scrub soft-errors and circumvent the permanent damage in the device. Besides the scheduling circuit is itself fault-tolerant, ATB is aware of the occurring faults in the silicon substrate of the chip, leading to a very reliable “fault-tolerant square scheduling”.
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Iturbe, X., Benkrid, K., Arslan, T., Azkarate, M., Martinez, I. (2011). A (Fault-Tolerant)2 Scheduler for Real-Time HW Tasks. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_9
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DOI: https://doi.org/10.1007/978-3-642-19475-7_9
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