Abstract
The balance metric is a simple approach to estimate the performance of bandwidth-limited loop kernels. However, applying the method to modern multi-core architectures yields unsatisfactory results. This paper analyzes the influence of cache hierarchy design on performance predictions for bandwidth-limited loop kernels on current mainstream processors. We present a diagnostic model with improved predictive power, correcting the limitations of the simple balance metric. The importance of code execution overhead even in bandwidth-bound situations is emphasized.
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Treibig, J., Hager, G., Wellein, G. (2010). Complexities of Performance Prediction for Bandwidth-Limited Loop Kernels on Multi-Core Architectures. In: Wagner, S., Steinmetz, M., Bode, A., Müller, M. (eds) High Performance Computing in Science and Engineering, Garching/Munich 2009. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-13872-0_1
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DOI: https://doi.org/10.1007/978-3-642-13872-0_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-13871-3
Online ISBN: 978-3-642-13872-0
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