Abstract
This paper presents a technique for automatically generating cycle-approximate transaction level models (TLMs) for multi-process applications mapped to embedded platforms. It incorporates three key features: (a) basic block level timing annotation, (b) RTOS model integration, and (c) RTOS overhead delay modeling. The inputs to TLM generation are application C processes and their mapping to processors in the platform. A processor data model, including pipelined datapath, memory hierarchy and branch delay model is used to estimate basic block execution delays. The delays are annotated to the C code, which is then integrated with a generated SystemC RTOS model. Our abstract RTOS provides dynamic scheduling and inter-process communication (IPC) with processor- and RTOS-specific pre-characterized timing. Our experiments using a MP3 decoder and a JPEG encoder show that timed TLMs, with integrated RTOS models, can be automatically generated in less than a minute. Our generated TLMs simulated three times faster than real-time and showed less than 10% timing error compared to board measurements.
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Austin, T., Larson, E., Ernst, D.: Simplescalar: an infrastructure for computer system modeling. Computer 35(2), 59–67 (2002)
Bammi, J.R., Kruijtzer, W., Lavagno, L.: Software Performance Estimatioin Strategies in a System-Level Design Tool. In: CODES, San Diego, USA (2000)
Cai, L., Gerstlauer, A., Gajski, D.: Retargetable Profiling for Rapid, Early System-Level Design Space Exploration. In: DATE, San Diego, USA (June 2004)
Cho, Y., Zergainoh, N.-E., Choi, K., Jerraya, A.A.: Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. In: RSP, Porto Alegre, Brazil (2007)
Chung, M.-K., Na, S., Kyung, C.-M.: System-Level Performance Analysis of Embedded System using Behavioral C/C++ model. In: VLSI-TSA-DAT, Hsinchu, Taiwan (2005)
ESE: Embedded Systems Environment, http://www.cecs.uci.edu/~ese
Gajski, D.D., Zhu, J., Dömer, R., Gerstlauer, A., Zhao, S.: SpecC: Specification Language and Design Methodology. Kluwer Academic Publishers, Dordrecht (2000)
Gerstlauer, A., Yu, H., Gajski, D.D.: Rtos modeling for system level design. In: Proceedings of the Design, Automation and Test in Europe (DATE) Conference, Munich, Germany (March 2003)
Grötker, T., Liao, S., Martin, G., Swan, S.: System Design with SystemC. Kluwer Academic Publishers, Dordrecht (2002)
Honda, S., et al.: RTOS-Centric Hardware/Software Cosimulator for Embedded System Design. Stockholm (2004)
Hwang, Y., Abdi, S., Gajski, D.: Cycle-approximate Retargetable Performance Estimation at the Transaction Level. In: DATE, Munich, Germany (March 2008)
Kempf, T., Karuri, K., Wallentowitz, S., Ascheid, G., Leupers, R., Meyr, H.: A SW Performance Estimation Framework for Early System-Level-Design using Fine-grained Instrumentation. In: DATE, Munich, Germany (March 2006)
Lajolo, M., Lazarescu, M., Sangiovanni-Vincentelli, A.: A Compilation-based Software Estimation Scheme for Hardware/Software Co-simulation. In: CODES, Rome (1999)
Lee, J.-Y., Park, I.-C.: Time Compiled-code Simulation of Embedded Software for Performance Analysis of SOC design. In: DAC, New Orleans, USA (June 2002)
LLVM (Low Level Virtual Machine) Compiler Infrastructure Project, http://www.llvm.org
Posadas, H., et al.: RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model 10(4), 209–227 (December 2005)
Russell, J.T., Jacome, M.F.: Architecture-level Performance Evaluation of Component-based Embedded Systems. In: DAC, Anaheim, USA (June 2003)
Xilinx. OS and Libraries Document Collection (2006)
Xilinx. MicroBlaze Processor Reference Manual (2007)
Zabel, H., Müller, W., Gerstlauer, A.: Accurate RTOS modeling and analysis with SystemC. In: Ecker, W., Müller, W., Dömer, R. (eds.) Hardware Dependent Software: Principles and Practice (2009)
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Hwang, Y., Schirner, G., Abdi, S. (2009). Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support. In: Rettberg, A., Zanella, M.C., Amann, M., Keckeisen, M., Rammig, F.J. (eds) Analysis, Architectures and Modelling of Embedded Systems. IESS 2009. IFIP Advances in Information and Communication Technology, vol 310. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04284-3_7
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DOI: https://doi.org/10.1007/978-3-642-04284-3_7
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