Abstract
During a typical development process of an embedded application specific processor (ASIP), the architecture is implemented multiple times on different levels of abstractions. As a result of this redundant specification, certain inconsistencies may show up. For example, the implementation of an instruction in the simulator may differ from the HDL implementation. To detect such inconsistencies, we use register trace comparison. Our key contribution is a generic method for systematic trace synchronization. Therefore, we convert a micro-architectural trace into an architectural trace. This method considers pipeline hazards and non-uniform write latencies. To simplify the validation of a processor, we further have implemented an automatic validation environment that includes a tool which points the developer directly to erroneous instructions. The flow has been validated during the development of our CoreVA architecture for mobile applications.
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Keywords
- Processor Core
- Single Instruction Multiple Data
- Device Under Test
- Very Long Instruction Word
- Architecture Description Language
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References
Azevedo, R., Rigo, S., Bartholomeu, M., Araujo, G., Araujo, C., Barros, E.: The ArchC architecture description language and tools. Int. J. Parallel Program. 33, 453–484 (2005)
Burch, J., Dill, D.: Automatic verification of Pipelined Microprocessor Control. In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818, pp. 68–80. Springer, Heidelberg (1994)
Chang, Y., Lee, S., Park, I., Kyung, C.: Verification of a microprocessor using real world applications. In: DAC 1999, pp. 181–184 (1999)
Gonzalez, R.: Xtensa: A Configurable and Extensible Processor. IEEE Micro., 60–70 (2000)
Hosseini, A., Mavroidis, D., Konas, P.: Code generation and analysis for the functional verification of micro processors. In: DAC 1996, pp. 305–310 (1996)
Kalte, H., Porrmann, M., Rückert, U.: A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs. In: Proc. of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip, SoC (2002)
Kastens, U., Le, D., Slowik, A., Thies, M.: Feedback Driven Instruction-Set Extension. In: LCTES 2004 (2004)
Sawada, J., Hunt, W.: Trace Table Based Approach for Pipeline Microprocessor Verification. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, Springer, Heidelberg (1997)
Victor, D., Ludden, J., Peterson, R., Nelson, B., Sharp, W., Hsu, J., Chu, B., Behm, M., Gott, R., Romonosky, A., Farago, A.: Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems. IBM J. Res. Dev. 49, 541–553 (2005)
Yim, J., Hwang, Y., Park, C., Choi, H., Yang, W., Oh, H., Park, I., Kyung, C.-M.: A C-based RTL Design Verification Methodology For Complex Microprocessor. In: DAC 1997, pp. 83–88 (1997)
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© 2009 IFIP International Federation for Information Processing
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Dreesen, R., Jungeblut, T., Thies, M., Porrmann, M., Kastens, U., Rückert, U. (2009). A Synchronization Method for Register Traces of Pipelined Processors. In: Rettberg, A., Zanella, M.C., Amann, M., Keckeisen, M., Rammig, F.J. (eds) Analysis, Architectures and Modelling of Embedded Systems. IESS 2009. IFIP Advances in Information and Communication Technology, vol 310. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04284-3_19
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DOI: https://doi.org/10.1007/978-3-642-04284-3_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-04283-6
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