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CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey

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Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2009)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5657))

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Abstract

The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems require efficient video coding algorithms and corresponding adaptive high-performance computational platforms. The H.264/AVC video coding algorithms provide high enough compression efficiency to be utilized in these systems, and multimedia processors are able to provide the required adaptability, but the algorithms complexity demands for more efficient computing platforms. Heterogeneous (re-)configurable systems composed of multimedia processors and hardware accelerators constitute the main part of such platforms. In this paper, we survey the hardware accelerator architectures for Context-based Adaptive Binary Arithmetic Coding (CABAC) of Main and High profiles of H.264/AVC. The purpose of the survey is to deliver a critical insight in the proposed solutions, and this way facilitate further research on accelerator architectures, architecture development methods and supporting EDA tools. The architectures are analyzed, classified and compared based on the core hardware acceleration concepts, algorithmic characteristics, video resolution support and performance parameters, and some promising design directions are discussed. The comparative analysis shows that the parallel pipeline accelerator architecture seems to be the most promising.

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Author information

Authors and Affiliations

  1. Faculty of Electrical Engineering, Eindhoven University of Technology, The Netherlands

    Yahya Jan & Lech Jozwiak

Authors
  1. Yahya Jan
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  2. Lech Jozwiak
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Editor information

Editors and Affiliations

  1. Delft University of Technology, Mekelweg 4, 2628, Delft, CD, The Netherlands

    Koen Bertels  & Stephan Wong  & 

  2. Department of Electrical and Computer Engineering, University of Victoria, P.O. Box 3055, V8W 3P6, Victoria, BC, Canada

    Nikitas Dimopoulos

  3. Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.za Leonardo Da Vinci 32, 20133, Milan, Italy

    Cristina Silvano

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© 2009 IFIP International Federation for Information Processing

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Jan, Y., Jozwiak, L. (2009). CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. In: Bertels, K., Dimopoulos, N., Silvano, C., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2009. Lecture Notes in Computer Science, vol 5657. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03138-0_4

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  • DOI: https://doi.org/10.1007/978-3-642-03138-0_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-03137-3

  • Online ISBN: 978-3-642-03138-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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