Abstract
In synchronous circuit design, new levels of abstraction above RTL allow the designer to model, simulate, debug and explore various architectures more efficiently than before. These are known as transaction level modeling. The translation between signals at different levels of abstraction is performed by pieces of code called transactors, mainly for the purpose of simulation. This paper identifies a set of asynchronous abstractions suitable for asynchronous transaction level modeling. Based on these models, we show that asynchronous CSP-based transactors can bring many more benefits than their synchronous counterparts, while being simpler to describe. We show how they can be used to automatically generate complex SystemC templates and hardware-software links, and automatically build network-on-chip interfaces facilitating IP reuse in embedded systems. Tools were developed after the techniques described in this paper. They are used in a case study to describe an asynchronous IP from transaction levels to RTL, demonstrating the automatic generation of various complex parts of the design and the minimum amount of specifications required from the designer.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Moore, S., Taylor, G., Robinson, P., Mullins, R.: Point to Point GALS Interconnect. In: Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC’02) (2002)
Bainbridge, W.J., Furber, S.B.: CHAIN: A Delay Insensitive CHip Area INterconnect. IEEE Micro special issue on Design and Test of System on Chip 22(5), 16–23 (2002)
Parker, D.: Transactor generation using the CY language. SpiraTech Limited
TransactorWizard, http://www.sdvinc.com
Balarin, F., Passerone, R.: Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation. Design, Automation and Test in Europe (2006)
Property Specification Language: Reference Manual, http://www.accellera.org/pslv101.pdf
Hoare, C.A.R.: Communicating sequential processes. Comms. of the ACM 21(8) (1978)
Renaudin, M., Rigaud, J.B., et al.: TAST CAD Tools. ASYNC’02 Tutorial (2002)
Edwards, D., Bardsley, A.: Balsa: An Asynchronous Hardware Synthesis Language. The Computer Journal 45(1), 12–18
Balsamics, http://www.cs.manchester.ac.uk/apt/projects/tools/balsamics/transactors
Open Core Protocol International Partnership, http://www.ocpip.org
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Janin, L., Edwards, D. (2007). CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse. In: Gervasi, O., Gavrilova, M.L. (eds) Computational Science and Its Applications – ICCSA 2007. ICCSA 2007. Lecture Notes in Computer Science, vol 4707. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74484-9_14
Download citation
DOI: https://doi.org/10.1007/978-3-540-74484-9_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74482-5
Online ISBN: 978-3-540-74484-9
eBook Packages: Computer ScienceComputer Science (R0)