Abstract
With the end goal of implementing optimal Reed-Solomon error control decoders on FPGAs, we characterize the FPGA performance of several finite field multiplier designs reported in the literature. We discover that finite field multipliers optimized for VLSI implementation are not optimized for FPGA implementation. Based on this observation, we discuss the relative merits of each multiplier design and show why each does not perform well on FPGAs. We then suggest how to improve the performance of many finite field multiplier designs.
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Ahlquist, G.C., Nelson, B., Rice, M. (1999). Optimal Finite Field Multipliers for FPGAs. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_6
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DOI: https://doi.org/10.1007/978-3-540-48302-1_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
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