Abstract
In this work a novel approach to optimize digital integrated circuits yield with regards to speed, dynamic power and leakage power constraints is presented. The method is based on process parameter estimation circuits and adaptive body bias (ABB) and/or adaptive supply voltage (ASV) performed by an on-chip digital controller. The associated design flow allows to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the estimation circuits used, the proposed design flow. An application case study, referring to an industrial 0.13 ?m CMOS process is used to compare ABB and ASV techniques. It is shown that ABB technique is particularly effective at high working temperatures and allows a stronger yield improvement with respect to the ASV technique. In the presented study, yields originally below 18% are improved to 83% by means of ABB alone and to 97% using ABB and ASV jointly.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Narendra, S., Borkar, S., De, V., Antoniadis, D., Chandrakasan, A.: Scaling of stack effect and its application for leakage reduction. In: International Symposium on Low Power Electronics and Design 2001, pp. 195–200 (2001)
Chen, T., Naffziger, S.: Comparison of Adaptive Body Bias (ABB) and Adaptive Supply Voltage (ASV) for Improving Delay and Leakage Under the Presence of Process Variation. IEEE Trans. on VLSI Systems 11(5), 888–899 (2003)
Director, S.W., Feldman, P., Krishna, K.: Statistical Integrated Circuit Design. IEEE Journal of Solid-State Circuits 28(3), 193–202 (1993)
Zhang, Q., Liou, J., McMacken, J., Thomson, J., Payman, P.: Development of robust interconnect model based on design of experiments and multiobjective optimization. IEEE Trans. Electron Devices 48, 1885–1891 (2001)
Tschanz, J.W., Kao, J.T., Narendra, S.G., Nair, R., Antoniadis, D.A., Chandrakasan, A.P., De, V.: Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE Journal of Solid-State Circuits 37(11), 1396–1402 (2002)
Keshavarzi, A., Ma, S., Narendra, S., Bloechel, B., Mistry, K., Ghani, T., Borkar, S., De, V.: Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS Ics. In: International Symposium on Low Power Electronics and Design 2001, pp. 207–212 (2001)
Keshavarzi, A., Narendra, S., Bloechel, B., Borkar, S., De, V.: Forward Body Bias for Microprocessors in 130 nm Technology Generation and Beyond. In: Symposium on VLSI Circuits Digest of Technical Papers, June 13-15, pp. 312–315 (2002)
Narendra, S., Antoniadis, D., De, V.: Impact of using adaptive body bias to compensate dieto- die Vt variation on within-die Vt variation. In: International Symposium on Low Power Electronics and Design, pp. 229–232 (1999)
Leung, O.Y.-H., Yue, C.-W., Tsui, C.-Y., Cheng, R.S.: Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage. In: Proc. 1999 Int. Symp. Low-Power Electronics and Design, August 1999, pp. 36–41 (1999)
Schmitz, M.T., Al-Hashimi, B.M.: Energy minimization for processor cores using variable supply voltages. In: Proc. Institute of Electronic Engineers Workshop Systems on a Chip (September 2000)
Wei, G.-Y., Horowitz, M.: A fully digital, energy-efficient, adaptive power-supply regulator. IEEE J. Solid-State Circuits 34, 520–528 (1999)
Kim, J., Horowitz, R.: An efficient digital sliding controller for adaptive power supply regulation. In: Proc. 2001 Symp. VLSI Circuits Dig. Tech. Paper, June 2001, pp. 133–136 (2001)
Martin, S.M., Flautner, K., Mudge, T., Blaauw, D.: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. In: IEEE/ACM International Conference on Computer Aided Design, pp. 721–725 (2002)
Tschanz, J., Narendra, S., Nair, R., De, V.: Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. In: Symposium on VLSI Circuits Digest of Technical Papers, June 13-15, pp. 310–311 (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Olivieri, M., Scarana, M., Scotti, G., Trifiletti, A. (2004). Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_14
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive