Abstract
This paper presents an FPGA implementation of a channelizer based on digital filter bank with 2048 channels for satellite communications. The proposed architecture was simulated in Simulink and implemented on a Kintex-7 FPGA. The design was tested with a Universal Software Radio Peripheral (USRP).
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Acciarito, S., Giardino, D., Khanal, G.M., Re, M., Silvestri, F., Sergio, S. (2019). FPGA Implementation of a Channelizer with 2048 Channels Utilizing USRP-SDR Platform for Satellite Communications. In: De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2017. Lecture Notes in Electrical Engineering, vol 512. Springer, Cham. https://doi.org/10.1007/978-3-319-93082-4_4
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DOI: https://doi.org/10.1007/978-3-319-93082-4_4
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