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Advanced High Performance Computing for Big Data Local Visual Meaning

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Big Data and Visual Analytics

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Abstract

Being able to scale interactive analysis for big data clusters is gaining more importance with each passing day in our present time. For example, according to the Behaviors Questionnaire performed in 2015 by K.D. Nuggets, around one fourth of 459 participants tried to interpret data clusters that exceed 1 terabyte and 100 petabytes. One of the subjects of previous studies is the Canonic Method, which is used to form the meanings of big data in a fast and efficient manner, because approximate responses given as based on sampling usually bring benefits as much as the response itself; and the sampling may also lessen the burden of cognitive confusion in meaning. As a result of previous studies conducted on database environments, extremely precious data have been obtained in terms of sampling and local visual inference; however, in the present study, firstly, the new methods and the system problems on the access to inference data have been focused on [1–4].

Today, data production is developing at an amazing speed. In our present day, the exponential technical developments, analogue sensor data, adaptive digital systems, scientific high-sensitivity sensors, smart devices and integral-theoretical models cause that data are produced at an extremely great speed. It is expected that global data volume will grow at a speed of 40-fold each year and reach 44 zettabytes by 2020 [5]. The term “big data” has been produced in order to cope with the volume, speed and variety of the data produced, and to make sense of this data trend that is developing day by day. Big data are becoming the new focal point of technology in many fields. A series of additional tools and mechanisms may be integrated to big data systems in order to obtain, store and process different data. These systems use the advantage of a tremendous parallel processing power for the purpose of performing complex conversions and analyses. On the other hand, designing and using a big data system intended for a certain application is not practical [6–7], because data come from more than one source that are heterogeneous and autonomous, and are in complex and changing relations with each other growing in an adaptive manner. In addition to these, the rise of big data applications in which data collection phenomenon is increasing at an amazing speed is beyond the capacity of today’s hardware and software platforms in terms of managing, storing and processing data within a reasonable time [6].

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References

  1. What was the largest dataset you analyzed/data mined? poll, KD nuggets. www.kdnuggets.com/polls/2015/largest-dataset-analyzed-data-mined.html (2015)

  2. Fisher, D.: Big data exploration requires collaboration between visualization and data infrastructures. In: Proc. Workshop on Human-in-the Loop Data Analytics (HILDA), article no. 16 (2016)

    Google Scholar 

  3. Hellerstein, J.M., et al.: Interactive data analysis: the control project. Computer. 32(8), 51–59 (1999)

    Article  Google Scholar 

  4. Kwon, B.C., Verma, J., Haas, P.J., Demiralp, Ç.: Sampling for scalable visual analytics, visualization viewpoints. IEEE Computer Society 0272–1716/17, January/February, pp. 100–108 (2017)

    Google Scholar 

  5. Turner, V., Gantz, J., Reinsel, D., Minton, S.: The digital universe of opportunities: rich data and the increase value of the internet of things. IDC Anal. Future (2014)

    Google Scholar 

  6. Hu, H., Wen, Y., Chua, T.S., Li, X.: Toward scalable systems for big data analytics: a technology tutorial. IEEE Access. 2, 652–687 (2014)

    Article  Google Scholar 

  7. Wu, X., Zhu, X., Wu, G.Q., Ding, W.: Data mining with big data. IEEE Trans. Knowl. Data Eng. 26(1), 97–107 (2014)

    Article  Google Scholar 

  8. Liu, Z., Heer, J.: The effects of interactive latency on exploratory visual analysis. IEEE Trans. Visual Comput. Graphics. 20, 2122–2131 (2014)

    Article  Google Scholar 

  9. Middlebrook, R.D.: Analog design: the academic view, technology trends, electronic, engineering times, pp. 87–88, December 17 (1990)

    Google Scholar 

  10. Toumazou, C., Moschytz, G., Gilbert, B.: Trade-Offs in Analog Circuit Design: The Designer’s Companion. Kluwer Academic, Dordrecht (2002.), ISBN 1-4020-7037-3

    Book  Google Scholar 

  11. Zebulum, R.S., Pacheco, M.A.C., Vellasco, M.M.: Evolutionary Electronics Automatic Design of Electronic Circuits and Systems by Genetic Algorithms, pp. 3–6. CRC, Boca Raton (2001), ISBN 0-8493-0865-8

    Google Scholar 

  12. Aksu, O.: Investigation of evolution hardware studies on analog circuits for designing healthcare systems. In: The Society for Design and Process Science (SDPS), Conference, Orlando, 4–6 December (2016)

    Google Scholar 

  13. Quentin, K.G., et al.: Tools for computer-aided design of multigigahertz supeconducting digital circuits. IEEE Trans. Appl. Supercond. 9(1), 18–38 (1999)

    Article  Google Scholar 

  14. Williams, J.: Analog circuit design: art, science and personalities, ISBN 978–0750696401, pp. 15–16 (1991)

    Google Scholar 

  15. Sarpeshkar, R.: Analog versus digital: extrapolating from electronics to neurobiology. Neural Comput. 10, 1601–1638 (1998)

    Article  Google Scholar 

  16. Aggarwal, V., Berggren, K., O’Reilly, U.: On the “evolvable hardware” approach to electronic design invention. In: Proceedings of the 2007 WEAH, IEEE Workshop on Evolvable and Adaptive Hardware (2007)

    Google Scholar 

  17. Koza, R.J., et al.: Evolutionary design of analog electrical circuits using genetic programming. In: Adaptive Computing in Design and Manufacture Conference (ACDM-98) (1998)

    Google Scholar 

  18. Franz, G.: Digital signal processor trends. IEEE Micro. 20(6), 52–59 (2000)

    Article  Google Scholar 

  19. Schlottmann, C.R., Abramson, D., Hasler, P.E.: A MITE-based translinear FPAA. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(1), 1–9 (2012)

    Article  Google Scholar 

  20. Aksu, O., Kalinli, A., Tanik, M.: Development and improvement of analog circuit design: an adjustable analog signal generation circuit approach. In: SDPS 2012 Conference, Berlin, 10–15 June (2012)

    Google Scholar 

  21. Platonov, A.: Analog transmission more efficient than digital: can it be and when? In: 2014 International Conference on IEEE Signals and Electronic Systems (ICSES), pp. 1–4, 11–13 September (2014)

    Google Scholar 

  22. Koza, R.J., et al.: Automatic creation of computer programs for designing electrical circuits using genetic programming. In: Computational Intelligence and Software Engineering. World Scientific Publishing, Singapore (1997)

    Google Scholar 

  23. Ellis, R., Yoo, H., Graham, D., Hasler, P., Anderson, D.: A continuous-time speech enhancement front-end for microphone inputs. In: Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. II–728–II–731, Phoenix, AZ (2002)

    Google Scholar 

  24. Balkir, S., Dundar, G., Ogrenci, S.: Analog VLSI Design Automation. CRC, Boca Raton (2003.), ISBN:978-0-8493-1090-4

    Google Scholar 

  25. Glelen, G., Sansen, W.: Symbolic analysis for automated design of analog integrated circuits. In: The Springer International Series in Engineering and Computer Science, ISBN 978-0792391616 (1991)

    Google Scholar 

  26. Nair, B.S.: Digital electronics and logic design. PHI Learning, Delhi. part 4-2,4-3, ISBN 978-8120319561 (2002)

    Google Scholar 

  27. Hornby, G.S., Sekanina, L., Haddow, P.C.: Evolvable systems: from biology to hardware: In: 8th International Conference, ICES 2008, Prague, Czech Republic, September 21–24 (2008)

    Google Scholar 

  28. Dobkin, B., Hamburger, J.: Analog circuit design, Newnes, vol. 3, pp. 38, ISBN 978-0128000014 (2014)

    Google Scholar 

  29. Eick, M., Graeb, H.E.: MARS: matching-driven analog sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8), 1145–1158 (2012)

    Article  Google Scholar 

  30. Hasler, P., Smith, P., Ellis, R., Graham, D., Anderson, D.V.: Biologically inspired auditory sensing system interfaces on a chip. In: 2002 IEEE Sensors Conference, Orlando, FL (2002)

    Google Scholar 

  31. Smith, P.D., Kucic, M., Ellis, R., Hasler, P., Anderson, D.V.: Mel–frequency cepstrum encoding in analog floating-gate circuitry. In: Proceedings of the International Symposium on Circuits and Systems, pp. IV–671–IV–674, Phoenix, AZ (2002)

    Google Scholar 

  32. Zhang, W., Li, Y., Liu, N.: An online evolvable Chebyshev filter based on immune genetic algorithm. In: Proceedings of the International Multi Conference of Engineers and Computer Scientists IMECS, Hong Kong, (19–21) March (2008)

    Google Scholar 

  33. Malcher, A., Falkowski, P.: Analog reconfigurable circuits. Int. J. Electron. Telecommun. 60, 15–26 (2014)

    Article  Google Scholar 

  34. Hall, T.S., Twigg, C.M., Hasler, P., Anderson, D.V.: Application performance of elements in a floating-gate FPAA, In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS ‘04, vol. 2, pp. II-589-92 (2004)

    Google Scholar 

  35. Hall, T.S., Twigg, C.M., Gray, J.D., Hasler, P., Anderson, D.V.: Large-scale field-programmable analog arrays for analog signal processing. IEEE Trans. Circuits Syst. Regul. Pap. 52(11), 2298–2307 (2005)

    Article  Google Scholar 

  36. Lohn, J.D., Colombano, S.P.: A circuit representation technique for automated circuit design. IEEE Trans. Evol. Comput. 3(3), 205–219 (1999)

    Article  Google Scholar 

  37. Aksu, O., Kalınlı, A.: Development and improvement of analog circuit design: a message passing interface parallel computing approach with genetic algorithms. Soc. Des. Process Sci. (SDPS). 14(3), 37–52 (2010)

    Google Scholar 

  38. Bennett III, H.F., et al.: Automatic Synthesis, Placement and Routing of an Amplifier Circuit by Means of Genetic Programming. FX Palo Alto Laboratory, Palo Alto, CA (2000)

    Book  Google Scholar 

  39. Koza, J.R., et al.: Automated design of both the topology and sizing of analog electrical circuits using genetic programming. In: Gero, J.S., Sudweeks, F. (eds.) Artificial Intelligence in Design ‘96, pp. 151–170. Kluwer Academic, Dordrecht (1996)

    Chapter  Google Scholar 

  40. Grimbleby, J.B.: Automatic analogue circuit synthesis using genetic algorithms. In: IEEE Proceedings Circuits Devices and Systems, vol. 147, no. 6 (2000)

    Google Scholar 

  41. Brambilla, A., D’Amore, D.: The simulation errors introduced by the SPICE transient analysis. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. 40(1), 57–60 (1993)

    Article  MATH  Google Scholar 

  42. Wojcikowski, M., Glinianowicz, J., Bialko, M.: System for optimisation of electronic circuits using genetic algorithm. In: Proceedings of the Third IEEE International Conference on Electronics, Circuits, and Systems, ICECS ‘96, vol. 1, pp. 247–250 (1996)

    Google Scholar 

  43. Reiser, C., et al.: Dynamically reconfigurable analog/digital hardware-implementation using FPGA and FPAA technologies. J. Circuits Syst. Comput. World Sci Pub (1998)

    Google Scholar 

  44. Ganesan, S., Vemuri, R.: A methodology for rapid prototyping of analog systems. In: 1999 (ICCD ‘99) International Conference on Computer Design, pp. 482–488 (1999)

    Google Scholar 

  45. Zebulum, R., Sinohara, H., Vellasco, M., Santini, C., Pacheco, M., Szwarcman, M.: A reconfigurable platform for the automatic synthesis of analog circuits. In: The Second NASA/DoD Workshop on Evolvable Hardware, Proceedings, pp. 91–98 (2000)

    Google Scholar 

  46. Stoica, A., Keymeulen, D., Zebulum, R., Thakoor, A., Daud, T., Klimeck, Y., Tawel, R., Duong, V.: Evolution of analog circuits on field programmable transistor arrays. In: The Second NASA/DoD Workshop on Evolvable Hardware, Proceedings, pp. 99–108 (2000)

    Google Scholar 

  47. Grimbleby, J.B.: Automatic analogue circuit synthesis using genetic algorithms. IEEE Proc. Circuits Devices Syst. 147(6), 319–323 (2000)

    Article  Google Scholar 

  48. Zebulum, R.S., Vellasco, M., Pacheco, M.A., Sinohara, H.T.: Evolvable hardware: on the automatic synthesis of analog control systems. In: Aerospace Conference Proceedings, IEEE, vol. 5, pp. 451–463 (2000)

    Google Scholar 

  49. Long, J.D., et al.: A parallel genetic algorithm for automated electronic circuit design (2000)

    Google Scholar 

  50. Paulino, N., Goes, J., Steiger-Garcao, A.: Design methodology for optimization of analog building blocks using genetic algorithms. In: The 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, vol. 5, pp. 435–438 (2001)

    Google Scholar 

  51. Goh, C., Li, Y.: GA Automated design and synthesis of analog circuits with practical constraints. In: Proceedings of the 2001 Congress on Evolutionary Computation, vol. 1, pp. 170–177 (2001)

    Google Scholar 

  52. Stoica, G., Xin, R.S., Zebulum, M.I., Ferguson, D.: Evolution-based automated reconfiguration of field programmable analog devices. In: IEEE International Conference on Field-Programmable Technology (FPT), pp. 403–406 (2002)

    Google Scholar 

  53. Sanahuja, R., Barcons, V., Balado, L., Figueras, J.: Experimental test bench for mixed-signal circuits based on FPAA devices. In: Conference on Design of Circuits and Integrated Systems (DCIS), pp. 344–349 (2003)

    Google Scholar 

  54. Colsell, S., Edwards, R.: Adaptive real-time systems and the FPAA. In: Field Programmable Logic and Application, Lecture Notes in Computer Science, vol. 2778, pp. 944–947. Springer Berlin, Heidelberg (2003.), 978-3-540-40822-2

    Google Scholar 

  55. Santini, C.C., Amaral, J.F.M., Pacheco, M.A.C., Tanscheit, R.: Evolvability and reconfigurability. In: IEEE International Conference Field-Programmable Technology, Proceedings, pp. 105–112 (2004)

    Google Scholar 

  56. McConaghy, T., Eeckelaert, T., Gielen, G.: CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming. In: Design, Automation and Test in Europe, vol. 2, pp. 1082–1087 (2005)

    Google Scholar 

  57. Okada, K., Yoshihara, Y., Sugawara, H., Masu, K.: Reconfigurable RF circuit design. In: 18th Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 683–686 (2005)

    Google Scholar 

  58. Ghali, K., Dorie, L., Hammami, O.: Dynamically reconfigurable analog circuit design automation through multiobjective optimization and direct execution. In: 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005, pp. 1–4 (2005)

    Google Scholar 

  59. Hall, T., Twigg, C.: Field-programmable analog arrays enable mixed-signal prototyping of embedded systems. In: 48th Midwest Symposium on Circuits and Systems, vol. 1, pp. 83–86 (2005)

    Google Scholar 

  60. Zhao, S., Jiao, L., Zhao, J., Wang, Y.: Evolutionary design of analog circuits with a uniform-design based multi-objective adaptive genetic algorithm. In: NASA/DoD Conference on Evolvable Hardware, pp. 26–29 (2005)

    Google Scholar 

  61. Jin’no K.: An automated circuit design procedure by means of genetic programming. In: 2005 International Symposium on Nonlinear Theory and its Applications (NOLTA2005) Bruges, Belgium, pp. 194–197, October 18–21 (2005)

    Google Scholar 

  62. Terry, M. A., Marcus, J., Farrell, M., Aggarwal, V., O’Reilly, U.: GRACE: generative robust analog circuit exploration. In: Applications of Evolutionary Computing EvoWorkshops2006 EvoBIO EvoCOMNET EvoHOT EvoIASP EvoInteraction EvoMUSART EvoSTOC, vol. 3907, pp. 332–343 (2006)

    Google Scholar 

  63. Li, Y., Cho, Y.: Parallel genetic algorithm for SPICE model parameter extraction. In: Parallel and Distributed Processing Symposium, IPDPS 20th International, pp. 8, 25–29 April (2006)

    Google Scholar 

  64. Ferlin, E.P., Lopes, H.S., Lima, C.R.E., Cichaczewski, E.: Reconfigure parallel architecture for genetic algorithms: application to the synthesis of digital circuits. In: Third International Workshop, ARC 2007, Brazil, pp. 326–336, March 27–29 (2007)

    Google Scholar 

  65. Gyorok, G.: Self organizing analogue circuit by Monte Carlo method. In: LINDI International Symposium on Logistics and Industrial Informatics, pp. 37–40, 13–15 September (2007)

    Google Scholar 

  66. Aggarwal, V., Berggren, K., O’Reilly, U.: On the evolvable hardware approach to electronic design invention. In: 2007 WEAH IEEE Workshop on Evolvable and Adaptive Hardware, pp. 46–54, 1–5 April (2007)

    Google Scholar 

  67. Petre, C., Schlottmann, C., Hasler, P.: Automated conversion of Simulink designs to analog hardware on an FPAA. In: IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp. 500–503, 18–21 May (2008)

    Google Scholar 

  68. Potirakis, S.M., Deli, J., Rangoussi, M.: steady-state and transient evaluation of FPAA implemented analog filters using a MLS system analyzer. In: 16th International Conference on Systems, Signals and Image Processing, IWSSIP 2009, pp. 1–8, 18–20 June (2009)

    Google Scholar 

  69. Krishnamurthy, V., Kim, B.: Development of analog circuit design automation tool, Southeastcon, SOUTHEASTCON ‘09, IEEE, pp. 236–241, 5–8 March (2009)

    Google Scholar 

  70. Koziol, S., et al.: Hardware and software infrastructure for a family of floating-gate based FPAAs. In: Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2794–2797, May 30–June 2 (2010)

    Google Scholar 

  71. Visan, D.A., Lita, I., Jurian, M., Cioc, I.B.: Simulation and implementation of adaptive and matched filters using FPAA technology. In: 2010 IEEE 16th International Symposium for Design and Technology in Electronic Packaging (SIITME), pp. 177–180, 23–26 September (2010)

    Google Scholar 

  72. Martins, R., Lourenco, N., Horta, N.: LAYGEN II—automatic layout generation of analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11), 1641–1654 (2013)

    Article  Google Scholar 

  73. Haji Ali, M.S., Shaker, M.M., Salih, T.A.: Design and implementation of a dynamic analog matched filter using FPAA technology. IEEE J. Solid State Circuits. 23(6), 1298–1308 (2008)

    Google Scholar 

  74. Anadigm, Inc. http://www.anadigm.com

  75. Aksu, O.: Investigation of evolution hardware studies on analog circuits for rapid prototyping and proposal a new model, ELECO, pp. 147–155, Bursa (2016)

    Google Scholar 

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Authors and Affiliations

  1. University of Alabama at Birmingham, Birmingham, AL, USA

    Ozgur Aksu

  2. Erciyes University, Kayseri, Turkey, USA

    Ozgur Aksu

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Editors and Affiliations

  1. Department of Computer Science, Texas A&M University-Commerce, Commerce, Texas, USA

    Sang C. Suh

  2. Department of Electrical and Computer Engineering, The University of Alabama at Birmingham, Birmingham, Alabama, USA

    Thomas Anthony

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Aksu, O. (2017). Advanced High Performance Computing for Big Data Local Visual Meaning. In: Suh, S., Anthony, T. (eds) Big Data and Visual Analytics. Springer, Cham. https://doi.org/10.1007/978-3-319-63917-8_8

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  • DOI: https://doi.org/10.1007/978-3-319-63917-8_8

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