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Dependability Threats

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Dependable Multicore Architectures at Nanoscale

Abstract

This chapter discusses dependability threads for modern integrated circuits that affect both their correct operation and performance. The text provides an overview of fault/error models adopted in methodologies for dependability assessment, analysis, and mitigation. Faults are categorized based on their applicability in the various abstraction layers. Their applicability to modern design trends such as FPGAs and NoCs is also presented. Furthermore, models for emerging and future dependability issues are discussed in the same rationale. In particular, special attention is given to those issues that typically arise during the operational life of the devices, causing either transient, intermittent or permanent failures, including aging and wear-out effects that directly affect their lifetime.

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Authors and Affiliations

  1. Politecnico di Milano, DEIB, P.zza L. da Vinci, 32, 20133, Milano (MI), Italy

    Cristiana Bolchini & Antonio Miele

  2. University of Cyprus, 75 Kallipoleos Avenue, 1678, Nicosia, Cyprus

    Maria K. Michael

  3. University of Nicosia, 46 Makedonitissas Avenue, 2414, Nicosia, Cyprus

    Stelios Neophytou

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  1. Cristiana Bolchini
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  2. Maria K. Michael
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  3. Antonio Miele
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  4. Stelios Neophytou
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Correspondence to Cristiana Bolchini .

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  1. Department of Electronic Engineering, University of Rome Tor Vergata, Rome, Italy

    Marco Ottavi

  2. Department of Informatics and Telecommunications, National and Kapodistrian University of Athens, Athens, Greece

    Dimitris Gizopoulos

  3. National Inter-University Consortium for Telecommunications (CNIT), Rome, Italy

    Salvatore Pontarelli

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Bolchini, C., Michael, M.K., Miele, A., Neophytou, S. (2018). Dependability Threats. In: Ottavi, M., Gizopoulos, D., Pontarelli, S. (eds) Dependable Multicore Architectures at Nanoscale. Springer, Cham. https://doi.org/10.1007/978-3-319-54422-9_2

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