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Custom Multi-cache Architectures

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Separation Logic for High-level Synthesis

Part of the book series: Springer Theses ((Springer Theses))

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Abstract

FPGAs allow the implementor to tailor the interface to off-chip memory and the on-chip/off-chip memory hierarchy according to the requirements of the application. This chapter presents a high-level synthesis design aid that leverages a memory access analysis of the application to automatically synthesise an application-specific high-performance memory hierarchy.

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Notes

  1. 1.

    We focus on integer or fixed-point systems and ignore non-associativity caused by floating-point representations.

  2. 2.

    We use 32 kbits in a Xilinx 36K-RAM block to store user data.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Imperial College London, London, UK

    Felix Winterstein

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  1. Felix Winterstein
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Correspondence to Felix Winterstein .

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Winterstein, F. (2017). Custom Multi-cache Architectures. In: Separation Logic for High-level Synthesis. Springer Theses. Springer, Cham. https://doi.org/10.1007/978-3-319-53222-6_5

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  • DOI: https://doi.org/10.1007/978-3-319-53222-6_5

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-53221-9

  • Online ISBN: 978-3-319-53222-6

  • eBook Packages: EngineeringEngineering (R0)

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