Abstract
The sample-and-hold circuit or track-and-hold circuit performs the sampling operation. These circuits have to operate at the highest signal levels and speeds, which makes their design a challenge. The chapter discusses first the specific metrics for these circuits, such as pedestal step, droop time, and hold-mode feed-through. The different elements: switch, capacitor, and buffer are discussed. Some architectures and often applied implementation schemes are shown. The trade-off between noise and distortion requires a careful balance to achieve the optimum performance.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
For convenience reasons the switch is assumed to be implemented as an NMOS transistor, unless otherwise stated. Conduction takes place with a positive gate voltage.
- 2.
A relation seems likely with the tales on Baron von Mŭnchhausen, who pulled himself up by his bootstraps, and “booting” of computers.
- 3.
The word “source” is used for the device terminal with the arrow in the schematic, irrespective of the voltage.
- 4.
The so-called noise-excess factor is disputed, although some correction for the shape of the inversion layer may be applicable.
- 5.
Rule of thumb means here that this is a good level to start the discussion, various topologies give different results.
- 6.
The four-diode circuit is widely used for rectifying ac-signals under the name Grätz-bridge.
- 7.
See also [46] for an elementary discussion on distortion in analog circuits.
- 8.
A bipolar circuit is simple to analyze, of course the same holds for an MOS circuit.
- 9.
Contributions from higher-order terms are not included.
Bibliography
ITRS (1994–2013) The international technology roadmap for semiconductors. Last revision was in 2013, now seven focus topics. Updates: http://www.itrs2.net
Crols J, Steyaert M (1994) Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages. IEEE J Solid-State Circuits 29:936–942
Baschirotto A, Castello R (1997) A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing. IEEE J Solid-State Circuits 32:1979–1986
Dickson J (1976) On-chip high-voltage generation MNOS integrated circuits using an improved voltage multiplier technique. IEEE J Solid-State Circuits 11:374–378
Knepper RW (1978) Dynamic depletion mode: an E/D mosfet circuit method for improved performance. IEEE J Solid-State Circuits 13:542–548
Abo AM, Gray PR (1999) A 1.5-V, 10-bit, 14.3-MS/s CMOS pipe-line analog-to-digital converter. IEEE J Solid-State Circuits 34:599–606
Limotyrakis S, Kulchycki SD, Su DK, Wooley BA (2005) A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. IEEE J Solid-State Circuits 40:1057–1067
Keramat A, Tao Z (2000) A capacitor mismatch and gain insensitive 1.5-bit/stage pipelined A/D converter. In: Proceedings of the 43rd IEEE midwest symposium on circuits and systems, pp 48–51
Yang W, Kelly D, Mehr I, Sayuk MT, Singer L (2001) A 3-V 340-mW 14-b 75-MS/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J Solid-State Circuits 36:1931–1936
Song BA, Tompsett MF, Lakshmikumar KR (1988) A 12-bit 1-MS/s capacitor error-averaging pipelined A/D converter. IEEE J Solid-State Circuits 23:1324–1333
Gregoire BR, Moon U (2008) An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain. IEEE J Solid-State Circuits 43:2620–2630
Wakimoto T, Akazawa Y (1993) Circuits to reduce distortion in the diode-bridge track-and-hold. IEEE J Solid-State Circuits 28:384–387
Vorenkamp P, Verdaasdonk JPM (1992) Fully bipolar, 120-MS/s 10-b track-and-hold circuit. IEEE J Solid-State Circuits 27:988–992
Sansen W (1999) Distortion in elementary transistor circuits. IEEE Trans Circuits Syst II 46:315–325 4. Quantization
Liu C-C, Chnag S-J, Huang G-Y, Lin Y-Z (2010) A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid-State Circuits 45:731–740
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Pelgrom, M. (2017). Sample and Hold. In: Analog-to-Digital Conversion. Springer, Cham. https://doi.org/10.1007/978-3-319-44971-5_3
Download citation
DOI: https://doi.org/10.1007/978-3-319-44971-5_3
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-44970-8
Online ISBN: 978-3-319-44971-5
eBook Packages: EngineeringEngineering (R0)