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Sigma-Delta Modulation

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Analog-to-Digital Conversion

Abstract

The sigma-delta modulator is a specific algorithm to convert low-bandwidth signals into a digital data stream. In the first section the effects of oversampling are described both for the analog-to-digital converter and for the analog-to-digital converter. The next step is the noise shape topology. The feedback mechanism that is applied to the quantization errors allows to free a fraction of the bandwidth of this error energy. The basic mechanisms in the noise shaper are applied to show the effects of increasing the oversample rate and increasing the order of the feedback filter. A similar approach is adopted to deal with the sigma-delta topology. The time-discrete implementation allows to design first and second order modulators. The main extension towards higher orders is found in the cascaded sigma-delta modulator. The time-continuous sigma-delta modulators use simple transconductance-capacitor filters and their properties differ in a number of aspects from the time-discrete variants. Some implementation aspects are given. The discussion on the advantages of multi-bit conversion is summarized.

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Notes

  1. 1.

    As mentioned in Chap. 4 quantization errors specifically of low-resolution quantizers are not noise, but folded distortion products. With the introduction of the “white noise” model for quantization errors, the incorrect terms “noise” and “noise shaper” have become an accepted description.

  2. 2.

    Formula [8, formula 300] is here useful as pointed out by V. Zieren.

  3. 3.

    Is the term “sigma-delta” or “delta-sigma” more correct? Inose [305] uses in 1962 delta-sigma. The opposing argument is that the basic form was originally a delta-modulator which was extended with an summing function: a sigma-delta modulator.

  4. 4.

    More language issues: “modulator” or “converter.” In this book the circuitry around the quantizer is referred to as the modulator. The same circuit is called a converter if its system function is the dominant feature.

  5. 5.

    Many authors have published books on sigma-delta modulation, still the ultimate text has not been written. Books on this subject tend to be too mathematical, too magical, or both. First spend an hour with your upcoming purchase, before you decide! Also recommended for this book.

  6. 6.

    In the audio range these components are audible and are called “whistles.” Trained listeners can hear idle tones down to 100 dB below full-signal.

  7. 7.

    At this introductory point of the description, the variable z is used implying time-discrete behavior. In the following sections a more clear distinction between time-discrete and time-continuous implementations is made.

  8. 8.

    Normally a designer will try to use maximum signals throughout the entire circuit. In case scaled signals are used in some part of the circuit the value of V i must be scaled as well.

  9. 9.

    Variants exist where other analog-to-digital converters are used to digitize the quantization error [321], without much limitation.

Bibliography

  1. Beyer WH (1987) CRC standard mathematical tables, 28th edn. CRC Press, Boca Raton. ISBN:0-8493-0628-0

    MATH  Google Scholar 

  2. van den Enden AWM, Verhoeckx NAM (1989) Discrete time signal processing, an introduction. Prentice Hall, Englewood Cliffs. ISBN:0-132-167557

    Google Scholar 

  3. Barkin DB, Lin ACY, Su DK, Wooley BA (2004) A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering. IEEE J Solid-State Circuits 39:585–593

    Article  Google Scholar 

  4. Carley L (1989)A noise-shaping coder topology for 15+ bit converters. IEEE J Solid-State Circuits 24:267–273

    Google Scholar 

  5. Straayer MZ, Perrott MH (2008) A 12-Bit, 10-MHz bandwidth, continuous-time ADC with a 5-Bit, 950-MS/s VCO-based quantizer. IEEE J Solid-State Circuits 43:805–814

    Article  Google Scholar 

  6. de Jager F (1952) Delta modulation, a method of PCM transmission using the 1-unit code. Philips Res Rep 7:442–466

    Google Scholar 

  7. Cutler C (1960) Transmission systems employing quantization. U.S. Patent 2-927-962

    Google Scholar 

  8. Widrow B (1956) A study of rough amplitude quantization by means of Nyquist sampling theory. IRE Trans Circuit Theory CT-3:266–276

    Article  Google Scholar 

  9. Inose H, Yasuda Y, Murakami J (1962) A telemetering system by code modulation- \(\Delta \Sigma\) modulation. IRE Trans Space Electron Telem SET-8:204–209; or Proc IEEE 51:1524–1535 (1963)

    Google Scholar 

  10. Schreier R, Temes GC (2004) Understanding delta-sigma data converters. Wiley, New York. ISBN:0-471-46585–2

    Google Scholar 

  11. de la Rosa JM (2011) Sigma-delta modulators: tutorial overview, design guide, and state-of-the-art survey. IEEE Trans Circuits Syst I 58:1–21

    Article  MathSciNet  Google Scholar 

  12. de la Rosa JM, Schreier R, Pun K-P, Pavan S (2015) Next-generation delta-sigma converters: trends and perspectives. IEEE J Emerging Sel Top Circuits Syst 5:484–499

    Article  Google Scholar 

  13. Naus PJA, Dijkmans EC (1988) Low signal level distortion in sigma-delta modulators. In: 84th convention of the audio engineering society, Paris

    Google Scholar 

  14. Bonizzoni E, Pena Perez A, Maloberti F, Garcia-Andrade M (2008) Third-order sigma-delta modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW. In: European solid-state circuits conference, pp 218–221

    Google Scholar 

  15. Gambini S, Rabaey J (2007) A 100-kS/s 65-dB DR sigma-delta ADC with 0.65V supply voltage. In: 33th European solid state circuits conference, pp 202–205

    Google Scholar 

  16. Vleugels K, Rabii S, Wooley BA (2001) A 2.5 v sigma-delta modulator for broadband communications applications. IEEE J Solid-State Circuits 36:1887–1889

    Article  Google Scholar 

  17. Chae Y, Han G (2009) Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator. IEEE J Solid-State Circuits 44:369–373

    Google Scholar 

  18. Hart A, Voinigescu SP (2009) A 1 GHz bandwidth low-pass sigma-delta ADC with 20–50 GHz adjustable sampling rate. IEEE J Solid-State Circuits 44:1401–1414

    Article  Google Scholar 

  19. Lee WL, Sodini CG (1987) A topology for higher order interpolative coders. In: Proceedings of the IEEE international symposium on circuits and systems, pp 459–462

    Google Scholar 

  20. Chao KC-H, Nadeem S, Lee WL, Sodini CG (1990) A higher order topology for interpolative modulators for oversampling A/D converters. IEEE Trans Circuits Syst 37:309–318

    Article  Google Scholar 

  21. Williams III LA, Wooley BA (1994) A third-order sigma-delta modulator with extended dynamic range. IEEE J Solid-State Circuits 29:193–202

    Article  Google Scholar 

  22. Marabelli S, Fornasari A, Malcovati P, Maloberti F (2005) An 80-MHz, 14-bit bandpass mash sigma-delta/pipeline A/D converter with 5 MHz bandwidth for third generation mobile communication systems. Measurement 37:320–327

    Article  Google Scholar 

  23. Williams L, Wooley B (1991) Third-order cascaded sigma-delta modulators. IEEE Trans Circuits Syst 38:489–498

    Article  Google Scholar 

  24. Christen T, Burger T, Huang Q (2007) A 0.13 μm CMOS EDGE/UMTS/WLAN tri-mode ADC with-92dB THD. In: International solid-state circuits conference, digest of technical papers, pp 240–241

    Google Scholar 

  25. Breems LJ, Rutten R, van Veldhoven RHM, van der Weide G (2007) A 56 mW continuous-time quadrature cascaded \(\Sigma \Delta\) modulator with 77 dB DR in a near zero-IF 20 MHz band. IEEE J Solid-State Circuits 42:2696–2705

    Article  Google Scholar 

  26. Kulchycki SD, Trofin R, Vleugels K, Wooley BA (2008) A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascaded sigma delta modulator. IEEE J Solid-State Circuits 43:796–804

    Article  Google Scholar 

  27. Gharbiya A, Johns DA (2009) A 12-bit 3.125 MHz bandwidth 0–3 MASH delta-sigma modulator. IEEE J Solid-State Circuits 44:2010–2018

    Article  Google Scholar 

  28. Chae YC, Souri K, Makinwa KAA (2013) A 6.3 μW 20bit incremental zoom-ADC with 6 ppm INL and 1 μV offset. IEEE J Solid-State Circuits 48:3019–3027

    Article  Google Scholar 

  29. Gönen B, Sebastiano F, van Veldhoven R, Makinwa KAA (2016) A 1.65 mW 0.16 mm2 dynamic zoom-ADC with 107.5 dB DR in 20 kHz BW. In: International solid-state circuits conference, digest of technical papers, pp 282–283

    Google Scholar 

  30. Kup BMJ, Dijkmans EC, Naus PJA, Sneep J (1991) A bit-stream digital-to-analog converter with 18-b resolution. IEEE J Solid-State Circuits 26:1757–1763

    Article  Google Scholar 

  31. Naus PJA, Dijkmans EC, Stikvoort EF, Holland DJ, Bradinal W (1987) A CMOS stereo 16-bit D/A converter for digital audio. IEEE J Solid-State Circuits 22:390–395

    Article  Google Scholar 

  32. Adams R, Nguyen KQ (1998) A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling. IEEE J Solid-State Circuits 33:1871–1878

    Article  Google Scholar 

  33. Colonna V, Annovazzi M, Boarin G, Gandolfi G, Stefani F, Baschirotto A (2005) A 0.22-mm2 7.25-mW per-channel audio stereo-DAC With 97-dB DR and 39-dB SNR. IEEE J Solid-State Circuits 40:1491–1498

    Article  Google Scholar 

  34. Benabes P, Keramat M, Kielbasa R (1997) A methodology for designing continuous-time sigma-delta modulators. In: Proceedings European design and test conference, EDTC -97, pp 46–50

    Google Scholar 

  35. van der Zwan EJ, Dijkmans EC (1996) A 0.2 mW CMOS \(\Sigma \Delta\) modulator for speech coding with 80 dB dynamic range. IEEE J Solid-State Circuits 31:1873–1880

    Article  Google Scholar 

  36. Breems LJ, Dijkmans EC, Huijsing JH (2001) A quadrature data-dependent DEM algorithm to improve image rejection of a complex \(\Sigma \Delta\) modulator. IEEE J Solid-State Circuits 36:1879–1886

    Article  Google Scholar 

  37. Dong Y, Yang W, Schreier R et al (2014) A continuous-time 0–3 MASH ADC achieving 88 dB DR with 53 MHz BW in 28 nm CMOS. IEEE J Solid-State Circuits 49:2868–2877

    Article  Google Scholar 

  38. Keller M, Buhmann A, Sauerbrey J, Ortmanns M, Manoli Y (2008) A comparative study on excess-loop-delay compensation techniques for continuous-time sigma-delta modulators. IEEE Trans Circuits Syst I 55:3480–3487

    Article  MathSciNet  Google Scholar 

  39. Bolatkale M (2013) High speed and wide bandwidth delta-sigma ADCs. PhD thesis, Technical University Delft. Available: http://repository.tudelft.nl

  40. Bolatkale M, Breems LJ, Rutten R, Makinwa KAA (2011) A 4 GHz continuous-time ADC with 70 dB DR and 74 dBFS THD in 125 MHz BW. IEEE J Solid-State Circuits 46:2857–2868

    Article  Google Scholar 

  41. Philips KJP (2005) \(\Sigma \Delta\) AD conversion for signal conditioning. PhD thesis, Technical University Eindhoven

    Google Scholar 

  42. Philips K, Nuijten PACM, Roovers RLJ, van Roermund AHM, Chavero FM, Pallares MT, Torralba A (2004) A continuous-time \(\Sigma \Delta\) ADC with increased immunity to interferers. IEEE J Solid-State Circuits 39:2170–2178

    Article  Google Scholar 

  43. Nguyen K, Adams R, Sweetland K, Chen H (2005) A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio. IEEE J Solid-State Circuits, 40:2408–2415

    Article  Google Scholar 

  44. Shettigar P, Pavan S (2012) A 15 mW 3.6GS/s CT-SD ADC with 36 MHz bandwidth and 83 dB DR in 90 nm CMOS. In: International solid-state circuits conference, digest of technical papers, pp 156–157

    Google Scholar 

  45. Shibata H, Schreier R, Yang W, Shaikh A, Paterson D, Caldwell T, Alldred D, Lai PW (2012) A DC-to-1GHz tunable RF SD ADC achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz using 550 mW. In: IEEE international solid-state circuits conference, digest of technical papers, pp 150–151

    Google Scholar 

  46. Adams RW (1986) Design and implementation of an audio 18-bit analog-to-digital converter using oversampling techniques. J Audio Eng Soc 34:153–166

    Google Scholar 

  47. Naus PJA, Dijkmans EC (1991) Multi-bit oversampled \(\Sigma \Delta\) A/D converters as front-end for CD players. IEEE J Solid-State Circuits 26:905–909

    Article  Google Scholar 

  48. van Veldhoven RHM, Minnis BJ, Hegt HA, van Roermund AHM (2002) A 3.3-mW \(\Sigma \Delta\) modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth. IEEE J Solid-State Circuits 37:1645–1652

    Article  Google Scholar 

  49. Ranjbar M et al (2010) A 3.1 mW continuous-time \(\Sigma \Delta\) modulator with 5-bit successive approximation quantizer for WCDMA. IEEE J Solid-State Circuits 45:1479–1491

    Article  Google Scholar 

  50. Lipshitz SP, Vanderkooy J (2001) Why 1-bit sigma-delta conversion is unsuitable for high-quality applications, paper 5395. In: 110th convention of the audio engineering society, Amsterdam

    Google Scholar 

  51. Silva PGR, Breems LJ, Makinwa K, Roovers R, Huijsing JH (2007) An IF-to-baseband \(\Sigma \Delta\) modulator for AM/FM/IBOC radio receivers with a 118 dB dynamic range. IEEE J Solid-State Circuits 42:1076–1089

    Article  Google Scholar 

  52. Ouzounov SF, Roza E, Hegt JA, van de Weide G, van Roermund AHM (2006) Analysis and design of high-performance asynchronous sigma delta modulators with binary quantizer. IEEE J Solid-State Circuits 41:588–596

    Article  Google Scholar 

  53. Vink J, van Rens J (1998) A CMOS multi-bit sigma-delta modulator for video applications. In: European solid-state circuits conference, pp 164–167

    Google Scholar 

  54. Park H, Nam KY, Su DK, Vleugels K, Wooley BA (2009) A 0.7-V 870-μW digital-audio CMOS sigma-delta modulator. IEEE J Solid-State Circuits 44:1078–1088

    Article  Google Scholar 

  55. Engelen J, van de Plassche R, Stikoort E, Venes A (1999) A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF. IEEE J Solid-State Circuits 34:1753–1764

    Article  Google Scholar 

  56. Schreier R, Abaskharoun N, Shibata H, Mehr I, Rose S, Paterson D (2006) A 375mW quadrature bandpass delta sigma ADC with 90dB DR and 8.5MHz BW at 44MHz. In: International solid-state circuits conference, digest of technical papers, pp 141–142

    Google Scholar 

  57. Ryckaert J et al (2009) A 2.4GHz low-power sixth-order RF bandpass SD converter in CMOS. IEEE J Solid-State Circuits 44:2873–2880

    Article  Google Scholar 

  58. Harrison J, Nesselroth M, Mamuad R, Behzad A, Adams A, Avery S (2012) An LC bandpass SD ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs. In: International solid-state circuits conference, digest of technical papers, pp 146–147

    Google Scholar 

  59. Chae H, Jeong J, Manganaro G, Flynn M (2012) A 12mW low-power continuous-time bandpass SD modulator with 58dB SNDR and 24MHz bandwidth at 200 MHz IF. In: International solid-state circuits conference, digest of technical papers, pp 148–149

    Google Scholar 

  60. Martens E et al (2012) RF-to-baseband digitization in 40 nm CMOS with RF bandpass \(\Delta \Sigma\) modulator and polyphase decimation filter. IEEE J Solid-State Circuits 47:990–1002

    Article  Google Scholar 

  61. Tao H, Khoury JM (1999) A 400-Ms/s frequency translating bandpass sigma-delta modulator. IEEE J Solid-State Circuits 34:1741–1752

    Article  Google Scholar 

  62. van Veldhoven RHM (2003) A triple-mode continuous-time \(\Sigma \Delta\) modulator with switched-capacitor feedback DAC for a GSM-EDGE/ CDMA2000/UMTS receiver. IEEE J Solid-State Circuits 38:2069–2076

    Article  Google Scholar 

  63. van der Zwan EJ, Philips K, Bastiaansen CAA (2000) A 10.7-MHz IF-to-baseband \(\Sigma \Delta\) A/D conversion system for AM/FM radio receivers. IEEE J Solid-State Circuits 35:1810–1819

    Article  Google Scholar 

  64. Bergveld HJ, van Kaam KMM, Leenaerts DMW, Philips KJP, Vaassen AWP, Wetzker G (2004) A low-power highly-digitized receiver for 2.4-GHz-band GFSK applications. In: IEEE radio frequency integrated circuits (RFIC) symposium, pp 347–350

    Google Scholar 

  65. Kavusi S, Kakavand H, El Gamal A (2006) On incremental sigma-delta modulation with optimal filtering. IEEE Trans Circuits Syst I: Fundam Theory Appl 53:1004–1015

    Article  MathSciNet  Google Scholar 

  66. Quiquempoix V, Deval P, Barreto A, Bellini G, Markus J, Silva J, Temes GC (2006) A low-power 22-bit incremental ADC. IEEE J Solid-State Circuits 41(7), 1562–1571

    Article  Google Scholar 

  67. Oike Y, Gamal AE (2013) CMOS image sensor with per-column \(\Sigma \Delta\) ADC and programmable compressed sensing. IEEE J Solid-State Circuits 48:318–328 11. Characterization and Specification

    Google Scholar 

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  1. HELMOND, Noord-Brabant, The Netherlands

    Marcel Pelgrom

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Pelgrom, M. (2017). Sigma-Delta Modulation. In: Analog-to-Digital Conversion. Springer, Cham. https://doi.org/10.1007/978-3-319-44971-5_10

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  • DOI: https://doi.org/10.1007/978-3-319-44971-5_10

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