Abstract
Reducing energy dissipations per function with the integrated circuit (IC) chips is always an appealing research topic. Techniques in the fundamental electronic device levels are being pursued besides of those in the architecture level. In this chapter, we introduce several device candidates with a common feature of steep slope as possible solutions for lower power computations. The ever increasing power densities with the complementary metal-oxide-semiconductor (CMOS) technologies and the behind reasons are reviewed first. Implications are reached that a device with steep slopes beyond the Boltzmann limitations helps. Then, several devices realizing steep slopes beyond that of the MOS field-effect-transistor (FET) technology are introduced, including the impact ionization FETs, the electro-mechanical FETs, the piezoelectric transistor, the ferroelectric FETs, the feedback FETs, and the tunneling FETs (TFETs). Afterward, we analyze the key features of the basic TFET operations and characteristics in details. Finally, several widely studied performance boosters for the TFET technology are also reviewed from device structures to doping and material engineering.
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Acknowledgement
This work was supported by the Hong Kong’s University Grant Committee via the Area of Excellence project AoE-P04-08. We would like to thank Prof. Cary Yang of Santa Clara University for his inputs on the steep slope devices.
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Zhang, L., Huang, J., Chan, M. (2016). Steep Slope Devices and TFETs. In: Zhang, L., Chan, M. (eds) Tunneling Field Effect Transistor Technology. Springer, Cham. https://doi.org/10.1007/978-3-319-31653-6_1
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