Abstract
Shrinking process technology poses a challenge to network-on-chip design for high performance and energy efficient router architecture to interconnect multiple cores on a chip. Because of its importance, several router micro-architectures are proposed in the literature. In this paper, we propose a novel router architecture, congestion aware switchable cycle adaptive deflection (CASCADE) router, which dynamically reconfigures itself from single-cycle buffer-less router to two-cycle minimally-buffered router, and vice-versa, based on the router congestion level. The CASCADE router employs congestion aware cycle switching and power-gating to achieve both power and performance efficiency under varying network loads. Experimental results show that, when compared to SLIDER, the state of the art minimally buffered deflection router, the CASCADE router achieves on average 19 % power reduction and 26 % flit latency reduction with marginal area overhead.
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Jonna, G.R., Thuniki, V.M., Mutyam, M. (2016). CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router. In: Hannig, F., Cardoso, J.M.P., Pionteck, T., Fey, D., Schröder-Preikschat, W., Teich, J. (eds) Architecture of Computing Systems – ARCS 2016. ARCS 2016. Lecture Notes in Computer Science(), vol 9637. Springer, Cham. https://doi.org/10.1007/978-3-319-30695-7_3
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DOI: https://doi.org/10.1007/978-3-319-30695-7_3
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