Abstract
News and trends in data storage have advanced to dominate technology and market headlines. They confirm many of the assessments in CHIPS 2020: The low-energy, high-speed static random-access memory (SRAM) with a 6–8-transistor cell is the digital chip function with the lowest supply voltage (<500 mV), the most advanced node on the nanometer roadmap (14 nm), and the potentially most robust nano-circuit due to its fully differential operation. The workhorse DRAM, dynamic RAM, advances only slowly, and, as predicted, is stuck at supply voltages >1 V and technology nodes >20 nm. The overall technology driver is the non-volatile NAND-Flash memory. While its minimum transistor length progresses to 16 nm, the vertical-channel, monolithic 3D transistor integration on-chip and the 3D TSV stacking of >30 chips have produced transistor densities of >1011/cm2 and memory densities >300 Gb/cm2, reaching the prediction in Fig. 11.1 of CHIPS 2020. The corollary of this achievement is a powerful technology arsenal for 3D integration , not only of memories, and for the extension of Moore’s law in terms of transistors/cm2. The non-volatile-memory alternatives to NAND Flash continue their competition in the battlefield of programming/writing with thermally induced resistance- or phase-changes. In terms of density as well as write and read speed, the resistive RAM (ReRAM), in the meantime, has made the biggest progress, and it has passed the PCM (phase-change memory). The process compatibility of the ReRAM as a back-end process to CMOS mainstream, as well as its speed and better data retention , make it the technology alternative for non-volatile RAM versus the NAND Flash.
The 6-transistor cell of a CMOS SRAM
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References
Song, T. et al.: A 14 nm FinFET 128 Mb 6T SRAM with Vmin-enhancement technique. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 232–233 (2014)
Hoefflinger, B.: Towards terabit memory, Chap. 11. In: Hoefflinger, B. (ed.) CHIPS 2020—A Guide to the Future of Nanoelectronics. Springer, Berlin (2012). doi:10.1007/978-3-64223096-7_11
Yabuuchi, M. et al.: 20 nm high-density single-port and dual-port SRAM’s with word-line voltage adjustment system for read/write assists. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 234–235
Chen, Y.H. et al.: A 16 nm 128 Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low VMIN applications, ibid. pp. 238–239
Oh, T.Y. et al.: A 3.2 Gb/s/pin 8 Gb 1.0 V LPDDR4 SDRAM with integrated ECC Engine for Sub-1 V DRAM core operation, ibid. pp. 430–431
Lee, D.U. et al.: A 1.2 V 8 Gb 8-channel 128 Gb/s high-bandwidth memory (HBM) Stacked DRAM with effective microbump I/O test methods using 29 nm process and TSV, ibid. pp. 432–433
Helm, M. et al.: A 128 Gb NAND-flash device in 16 nm planar technology, ibid. pp. 326–327
Choi, S. et al.: A 93.4 mm2 64 Gb NAND-flash memory with 16 nm CMOS technology, ibid. pp. 327–328
Park, K.T.: Three-dimensional 128 Gb vertical NAND flash memory with 24 WL-stacked layers and 50 MB/s high-speed programming, ibid. pp. 334–335
Im J.-W. et al.: A 128 Gb 3b/cell V-NAND Flash Memory with 1 Gb/s I/O Rate 2015 ISSCC Digest of Technical Papers, paper 7.2 (2015)
Handy, J.: An alternative kind of vertical 3D NAND string, published Nov. 8, 2013. http://thememoryguy.com/wp-content/uploads/2
2014 ISSCC Trends in Memory
Fackenthal, R.: A 16 Gb ReRAM with 200 MB/s/cell write and 1 GB/s/cell read in 27 nm technology, ibid. pp. 338–339
Chang, M.-F. et al.: A 3T1R nonvolatile TCAM using MLC ReRAM with sub-1 ns search time. In: 2015 ISSCC Digest of Technical Papers, paper 17.5, 2015
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Hoefflinger, B. (2016). Memory. In: Höfflinger, B. (eds) CHIPS 2020 VOL. 2. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-319-22093-2_11
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DOI: https://doi.org/10.1007/978-3-319-22093-2_11
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