Abstract
High throughput telecommunication systems such as long-haul optical transmission or passive optical networks require powerful error correcting codes in order to increase their optical budget. In such speed-constrained applications, the classical (255,239) Reed–Solomon code is gradually being replaced by more powerful forward error correction (FEC) schemes. In [1], turbo product codes (TPC) [2] are seen as the third generation FEC for optical transmission systems. TPC tend to be good candidates for emerging optical systems. The inherent parallel structure of the product code matrix confers to TPC a good ability for parallel decoding. Nevertheless, enhancing parallelism rate rapidly induces the use of a prohibitive amount of memory. Many architectural solutions were proposed to efficiently exploit parallelism in TPC decoding. Moreover, TPC decoding provides several level of parallelism and it is not always clear which level is the most efficient. In this chapter, several parallelism level of TPC decoding are identified. Each parallelism level is characterized in terms of the potential hardware efficiency that it may bring to the architecture. From this design space exploration, we focus on one efficient architecture that exploits different levels of parallelism.
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Notes
- 1.
A full iteration corresponds to a row-wise decoding followed by a column-wise decoding, which explains why the R′ matrix has to be updated 2I times.
- 2.
This assume that one is able to design a parallel processing unit that computes and select metrics in a single clock cycle.
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Leroux, C., Jego, C., Adde, P. (2015). Parallel Architectures for Turbo Product Codes Decoding. In: Chavet, C., Coussy, P. (eds) Advanced Hardware Design for Error Correcting Codes. Springer, Cham. https://doi.org/10.1007/978-3-319-10569-7_4
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