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Continuous-Time Delta-Sigma Modulators at High Sampling Rates

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High Speed and Wide Bandwidth Delta-Sigma ADCs

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

Abstract

This chapter describes the design of a continuous-time delta-sigma (CTΔΣ) modulator that can achieve a 125 MHz signal bandwidth (BW) with a 70 dB dynamic range (DR) in 45 nm CMOS. As explained in the previous chapter, various system-level non-idealities (noise, non-linearity, metastability and excess loop delay (ELD)), will limit its performance. Especially for a modulator which targets a wide bandwidth, these limitations pose a major challenge.

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Notes

  1. 1.

    MASH \(\Delta \Sigma \) modulators offer another route to increase signal BW [7]. However, the total output signal BW still depends on the signal BW of a single-loop modulator. Although this work focuses on extending the signal BW of a single-order modulator, the results can also be applied to increase the signal BW of MASH modulators.

  2. 2.

    CLK Q signal in Fig. 3.27b and RST signal in Fig. 4.4 represent the same signal.

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Authors and Affiliations

  1. NXP Semiconductors, Eindhoven, The Netherlands

    Muhammed Bolatkale & Lucien J. Breems

  2. Delft University of Technology, Delft, The Netherlands

    Kofi A. A. Makinwa

Authors
  1. Muhammed Bolatkale
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  2. Lucien J. Breems
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  3. Kofi A. A. Makinwa
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Bolatkale, M., Breems, L.J., Makinwa, K.A.A. (2014). Continuous-Time Delta-Sigma Modulators at High Sampling Rates. In: High Speed and Wide Bandwidth Delta-Sigma ADCs. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-05840-5_3

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  • DOI: https://doi.org/10.1007/978-3-319-05840-5_3

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  • Online ISBN: 978-3-319-05840-5

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