Abstract
Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and theoretical foundations presented in the previous chapters. In addition we show how DML logic can utilize the unique features of an ultra-thin body and box (UTBB) fully depleted silicon on insulator (FD-SOI) technology to achieve high-speed and energy-efficient designs for a wide range of supply voltage operations. This chapter starts with a brief comparison of DML and conventional static and dynamic CMOS logics for NAND–NOR chains in 28 nm FD-SOI. This basic analysis is followed by the construction of a real-life benchmark, a two-stage pipelined multiply-accumulate (MAC) circuit which was selected to assess the advantages of DML in terms of speed, energy, and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% with 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can reach up to 35% when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
D. Jacquet, F. Hasbani, P. Flatresse, R. Wilson, F. Arnaud, G. Cesana, T. Di Gilio, C. Lecocq, T. Roy, A. Chhabra, et al. A 3 ghz dual core processor arm cortex tm-a9 in 28 nm utbb fd-soi cmos with ultra-wide voltage range and energy efficiency optimization. IEEE J. Solid-State Circuits 49(4), 812–826 (2014)
P. Magarshack, P. Flatresse, G. Cesana, Utbb fd-soi: A process/design symbiosis for breakthrough energy-efficiency, in Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium (2013), pp. 952–957
D. Puschini, J. Rodas, E. Beigne, M. Altieri, S. Lesecq, Body bias usage in utbb fdsoi designs: A parametric exploration approach. Solid-State Electron. 117, 138–145 (2016)
S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan, A. Kumar, S.K. Gb et al., A 280mv-to-1.2 v wide-operating-range ia-32 processor in 32nm cmos, in 2012 IEEE International Solid-State Circuits Conference (IEEE, Piscataway, 2012), pp. 66–68
P. Flatresse, B. Giraud, J.-P. Noel, B. Pelloux-Prayer, F. Giner, D.-K. Arora, F. Arnaud, N. Planes, J. Le Coz, O. Thomas et al., Ultra-wide body-bias range ldpc decoder in 28nm utbb fdsoi technology, in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (IEEE, Piscataway, 2013), pp. 424–425
E. Beigne, I. Miro-Panades, Y. Thonnart, L. Alacoque, P. Vivet, S. Lesecq, D. Puschini, F. Thabet, B. Tain, K. Benchehida et al., A fine grain variation-aware dynamic vdd-hopping avfs architecture on a 32nm gals mpsoc, in 2013 Proceedings of the ESSCIRC (ESSCIRC) (IEEE, Piscataway, 2013), pp. 57–60
R. Taco, I. Levi, M. Lanuzza, A. Fish, Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm utbb fd-soi. Solid-State Electron. 117, 185–192 (2016)
A. Kaizerman, S. Fisher, A. Fish, Subthreshold dual mode logic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(5), 979–983 (2012)
M. Alioto, G. Palumbo, M. Pennisi, Understanding the effect of process variations on the delay of static and domino logic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(5), 697–710 (2009)
G. Desoli, N. Chawla, T. Boesch, S. Singh, E. Guidetti, F. De Ambroggi, T. Majo, P. Zambotti, M. Ayodhyawasi, H. Singh et al., 14.1 a 2.9 tops/w deep convolutional neural network soc in fd-soi 28nm for intelligent embedded systems, in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, Piscataway, 2017), pp. 238–239
T.T. Hoang, M. Sjalander, P. Larsson-Edefors, A high-speed, energy-efficient two-cycle multiply-accumulate (mac) architecture and its application to a double-throughput mac unit. IEEE Trans. Circ. Syst. I Regul. Pap. 57(12), 3073–3081 (2010)
M.C. Wen, S.J. Wang, Y.N. Lin, Low-power parallel multiplier with column bypassing. Electron. Lett. 41(10), 581–583 (2005)
I. Levi, A. Fish, Dual mode logic—design for energy efficiency and high performance. IEEE Access 1, 258–265 (2013)
M. Wen, S.J. Wang, Y.N. Lin, Low power parallel multiplier with column bypassing, in 2005 IEEE International Symposium on Circuits and Systems, vol. 2 (2005), pp. 1638–1641
P. Behrooz, Computer Arithmetic: Algorithms and Hardware Designs (Oxford University Press, Oxford, 2000), pp. 19:512,583–512,585
I. Levi, A. Kaizerman, A. Fish, Low voltage dual mode logic: Model analysis and parameter extraction. Microelectron. J. 44(6), 553–560 (2013)
I. Levi, A. Belenky, A. Fish, Logical effort for cmos-based dual mode logic gates. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(5), 1042–1053 (2013)
R.G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge, Near-threshold computing: Reclaiming moore’s law through energy efficient integrated circuits. Proc. IEEE 98(2), 253–266 (2010)
S.S. Mahant-Shetti, P.T. Balsara, C. Lemonds, High performance low power array multiplier using temporal tiling. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7(1), 121–124 (1999)
G. de Streel, D. Bol, Impact of back gate biasing schemes on energy and robustness of ulv logic in 28nm utbb fdsoi technology, in Proceedings of the 2013 International Symposium on Low Power Electronics and Design (IEEE Press, Piscataway, 2013), pp. 255–260
A.A. Vatanjou, T. Ytterdal, S. Aunet, 28 nm utbb-fdsoi energy efficient and variation tolerant custom digital-cell library with application to a subthreshold mac block, in 2016 MIXDES-23rd International Conference Mixed Design of Integrated Circuits and Systems (IEEE, Piscataway, 2016), pp. 105–110
H. Reyserhove, N. Reynders, W. Dehaene, Ultra-low voltage datapath blocks in 28nm utbb fd-soi, in 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, Piscataway, 2014), pp. 49–52
J.P. Cerqueira, M. Seok, Temporarily fine-grained sleep technique for near-and subthreshold parallel architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(1), 189–197 (2016)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Levi, I., Fish, A. (2021). Dual Mode Logic in FD-SOI Technology. In: Dual Mode Logic. Springer, Cham. https://doi.org/10.1007/978-3-030-40786-5_9
Download citation
DOI: https://doi.org/10.1007/978-3-030-40786-5_9
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-40785-8
Online ISBN: 978-3-030-40786-5
eBook Packages: EngineeringEngineering (R0)