Skip to main content

Towards a DML Optimized Synthesis

  • Chapter
  • First Online:
Dual Mode Logic
  • 320 Accesses

Abstract

In the previous chapter we discussed ways how to characterize DML cells into several libraries and use these with standard EDA tools. In this chapter we outline an optimized synthesis procedure for DML design. In a nutshell, this methodology involves changing certain steps within the tools. We present an algorithm for DML-optimized synthesis and show the implementation of this algorithm in Perl language. The synthesis results indicate that while this approach still has a significant room for improvement, it can boost performance gains and reduce the energy consumption of a design.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 16.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 99.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    Note that a designer can control and switch between the high-performance and low-energy modes on-the-fly.

  2. 2.

    The evaluation of both static and dynamic DML modes was applied to the same synthesized netlist, targeted in the dynamic mode.

References

  1. G. Yee, C. Sechen, Dynamic logic synthesis, in Custom Integrated Circuits Conference, 1997, Proceedings of the IEEE 1997 (IEEE, Piscataway, 1997), pp. 345–348

    Google Scholar 

  2. A. Pal, A. Mukherjee, Synthesis of two-level dynamic CMOS circuits, in IEEE Computer Society Workshop On VLSI’99. Proceedings (IEEE, Piscataway, 1999), pp. 82–92

    Google Scholar 

  3. D. Samanta, A. Pal, N. Sinha, Synthesis of high performance low power dynamic CMOS circuits, in Proceedings of the 2002 Asia and South Pacific Design Automation Conference (IEEE Computer Society, Washington, 2002), p. 99

    Google Scholar 

  4. B. Chappell, P. Saxena, J. Vendrell, X. Wang, P. Patra, M. Venkateshmurthy, S. Jain, H. Krishnamurthy, S. Hussain, S. Gupta et al., A system-level solution to domino synthesis with 2 GHz application, in 2012 IEEE 30th International Conference on Computer Design (ICCD) (IEEE Computer Society, Washington, 2002), pp. 164–164

    Google Scholar 

  5. D.M. Parmar, M. Sarma, D. Samanta, A novel approach to domino circuit synthesis, in 20th International Conference on VLSI Design, 2007. Held Jointly with 6th International Conference on Embedded Systems (IEEE, Piscataway, 2007), pp. 401–406

    Google Scholar 

  6. I. Levi, A. Fish, Dual mode logic – design for energy efficiency and high performance. Access IEEE 1, 258–265 (2013)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2021 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Levi, I., Fish, A. (2021). Towards a DML Optimized Synthesis. In: Dual Mode Logic. Springer, Cham. https://doi.org/10.1007/978-3-030-40786-5_8

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-40786-5_8

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-40785-8

  • Online ISBN: 978-3-030-40786-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics