Abstract
This chapter focuses on the granularity of the DML mode control. First, we describe a coarse-grain data-dependent controller that controls DML at the block level. We show that the operation mode of DML can be selected by critical path prediction architectures that considerably enhance performance. Then, we present a design example of a fine-grain, data-dependent controller that operates at the logic path level. The main goal of this chapter is to show that DML primitives can be utilized to make improvements at numerous abstraction levels even though these are more often associated with the gate level. We provide several examples illustrating how primitives can be controlled as a function of gate, path, block, and architecture level requirements.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
W. Kim, M.S. Gupta, G.-Y. Wei, D. Brooks, System level analysis of fast, per-core DVFS using on-chip switching regulators, in 2008 IEEE 14th International Symposium on High Performance Computer Architecture (IEEE, Piscataway, 2008), pp. 123–134
B.R. Zeydel, D. Baran, V.G. Oklobdzija, Energy-efficient design methodologies: high-performance VLSI adders. IEEE J. Solid State Circuits 45(6), 1220–1233 (2010)
H.Q. Dao, B.R. Zeydel, V.G. Oklobdzija, Energy optimization of pipelined digital systems using circuit sizing and supply scaling. IEEE Trans. Very Large Scale Integr. Syst. 14(2), 122 (2006)
W. Shen, Y. Cai, X. Hong, J. Hu, An effective gated clock tree design based on activity and register aware placement.IEEE Trans. Very Large Scale Integr. Syst. 18(12), 1639–1648 (2010)
J. Shinde, S. Salankar, Clock gating—a power optimizing technique for VLSI circuits, in 2011 Annual IEEE India Conference (IEEE, Piscataway, 2011), pp. 1–4
K. Roy, S.C. Prasad, Low-Power CMOS VLSI Circuit Design (Wiley, London, 2009)
M. Alioto, Ultra-low power VLSI circuit design demystified and explained: a tutorial. IEEE Trans. Circuits Syst. I: Reg. Papers 59(1), 3–29 (2012)
D. Bol et al., Robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 65/45 nm CMOS. J. Low Power Electron. Appl. 1(1), 1–19 (2011)
H. Zhang, J. Rabaey, Low-swing interconnect interface circuits, in Proceedings of the 1998 International Symposium on Low power Electronics and Design (ACM, New York, 1998), pp. 161–166
J.-S. Seo, H. Kaul, R. Krishnamurthy, D. Sylvester, D. Blaauw, A robust edge encoding technique for energy-efficient multi-cycle interconnect. IEEE Trans. Very Large Scale Integr. Syst. 19(2), 264–273 (2011)
S.J. Wilton, S.-S. Ang, W. Luk, The impact of pipelining on energy per operation in field-programmable gate arrays, in International Conference on Field Programmable Logic and Applications (Springer, Berlin, 2004), pp. 719–728
S. Kiamehr, M. Ebrahimi, M.S. Golanbari, M.B. Tahoori, Temperature-aware dynamic voltage scaling to improve energy efficiency of near-threshold computing. IEEE Trans. Very Large Scale Integr. Syst. 25(7), 2017–2026 (2017)
S. Höppner, Y. Yan, B. Vogginger, A. Dixius, J. Partzsch, F. Neumärker, S. Hartmann, S. Schiefer, S. Scholze, G. Ellguth et al., Dynamic voltage and frequency scaling for neuromorphic many-core systems, in 2017 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE, Piscataway, 2017), pp. 1–4
F. ur Rahman, V. Sathe, Quasi-resonant clocking: continuous voltage-frequency scalable resonant clocking system for dynamic voltage-frequency scaling systems. IEEE J. Solid State Circuits 53(3), 924–935 (2018)
S.B. Nasir, S. Sen, A. Raychowdhury, Switched-mode-control based hybrid LDO for fine-grain power management of digital load circuits. IEEE J. Solid State Circuits 53(2), 569–581 (2017)
S. Bang, W. Lim, C. Augustine, A. Malavasi, M. Khellah, J. Tschanz, V. De, 25.1 a fully synthesizable distributed and scalable all-digital LDO in 10 nm CMOS, in 2020 IEEE International Solid-State Circuits Conference-(ISSCC) (IEEE, Piscataway, 2020), pp. 380–382
F. Atallah, K. Bowman, H. Nguyen, J. Jeong, D. Yingling, Y. Sun, B. Appel, A. Polomik, M. Harinath, J. Morelli et al., 19.3 a 7 nm all-digital unified voltage and frequency regulator based on a high-bandwidth 2-phase buck converter with package inductors, in 2019 IEEE International Solid-State Circuits Conference-(ISSCC) (IEEE, Piscataway, 2019), pp. 316–318
S. Wimer, A. Albeck, I. Koren, A low energy dual-mode adder. Comput. Electr. Eng. 40(5), 1524–1537 (2014)
A. Kaizerman, S. Fisher, A. Fish, Subthreshold dual mode logic. IEEE Trans. Very Large Scale Integr. Syst. 21(5), 979–983 (2013)
I. Levi, A. Belenky, A. Fish, Logical effort for CMOS-based dual mode logic gates. IEEE Trans. Very Large Scale Integr. Syst. 22(5), 1042–1053 (2014)
I. Levi, A. Fish, Dual mode logic—design for energy efficiency and high performance. IEEE Access 1, 258–265 (2013)
I. Levi, O. Bass, A. Kaizerman, A. Belenky, A. Fish, High speed dual mode logic carry look ahead adder, in 2012 IEEE International Symposium on Circuits and Systems (IEEE, Piscataway, 2012), pp. 3037–3040
I. Levi, A. Kaizerman, A. Fish, Low voltage dual mode logic: model analysis and parameter extraction. Microelectron. J. 44(6), 553–560 (2013)
P. Behrooz, Computer Arithmetic: Algorithms and Hardware Designs, vol. 19 (Oxford University Press, 2000), pp. 512583–512585
K.C. Yeager, The Mips R10000 superscalar microprocessor. IEEE Micro 16(2), 28–41 (1996)
N.H.E. Weste, D.M. Harris, CMOS VLSI Design: A Circuit and System Perspective, 4th edn. (Pearson Education India, 2015)
R.P. Brent, H.-T. Kung, A regular layout for parallel adders. IEEE Trans. Comput. 3, 260–264 (1982)
J.L. Hennessy, D.A. Patterson, Computer Architecture: A Quantitative Approach (Elsevier, Amsterdam, 2011)
M.A. Franklin, T. Pan, Performance comparison of asynchronous adders, in Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems (IEEE, 1994)
F.-C. Cheng, S.H. Unger, M. Theobald, Self-timed carry-lookahead adders. IEEE Trans. Comput. 49(7), 659–672 (2000)
C.R. Kime, M. Morris Mano, Logic and computer design fundamentals (Prentice Hall, 2003)
I. Flores, The logic of computer arithmetic (1963)
A. De Gloria, M. Olivieri, Statistical carry lookahead adders. IEEE Trans. Comput. 45(3), 340–347 (1996)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Levi, I., Fish, A. (2021). DML Control. In: Dual Mode Logic. Springer, Cham. https://doi.org/10.1007/978-3-030-40786-5_6
Download citation
DOI: https://doi.org/10.1007/978-3-030-40786-5_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-40785-8
Online ISBN: 978-3-030-40786-5
eBook Packages: EngineeringEngineering (R0)