DML Energy-Delay Tradeoffs and Optimization

Abstract

As shown in the previous chapters, DML design provides very high energy-delay (E-D) optimization flexibility at the gate level. In this chapter, this flexibility is utilized to enhance the energy efficiency and performance of larger combinatorial circuits. In other words, we go up the design hierarchy to the (small) block level. The goal is to overview DML energy-delay tradeoffs for a composite block and present solutions that capitalize on the DML’s unique structure to achieve energy reduction and performance improvement. Specifically, we present critical-path-DML approaches that analyze the design’s critical paths and selectively allow for their operation in the fast, dynamic mode; by contrast, the energy reduction is achieved by static operation of the non-critical path of the system. These approaches are demonstrated on a Carry Look-Ahead DML adder example. The analysis is carried out as a function of supply voltage and the operand size of the adder (n).