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Low-Voltage DML

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Dual Mode Logic

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Abstract

This chapter examines DML performance, energy consumption, static noise margins, delay distribution, robustness, and other design metrics under low-voltage operation. It still focuses on the gate level and DML operations in subthreshold and near-threshold regions illustrated using the transregional model. Measurement results for fabricated test structures of a variety of DML benchmarks are presented, covering a wide range of operating conditions, supply voltages, etc. Whereas the last chapter mainly dealt with performance optimization of the DML dynamic mode, the main goal of this chapter is to provide an in-depth description of the superior performance of DML with regard to robustness and process variation immunity, and its operation at low voltages. The DML designs are compared to standard CMOS and (dynamic) domino to provide the reader with a better grasp of DML’s key features, compared to current alternatives.

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Notes

  1. 1.

    g was denoted by LE in the previous chapter. In this chapter, for conciseness, we use the original notations.

  2. 2.

    Note that domino logic in subthreshold voltages (e.g., 0.3 V) is not robust and does not function correctly under variations, as discussed below; therefore, we compare it here to a footed domino implementation to derive the LE parameters.

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Authors and Affiliations

  1. Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel

    Itamar Levi & Alexander Fish

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  1. Itamar Levi
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  2. Alexander Fish
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Levi, I., Fish, A. (2021). Low-Voltage DML. In: Dual Mode Logic. Springer, Cham. https://doi.org/10.1007/978-3-030-40786-5_4

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  • DOI: https://doi.org/10.1007/978-3-030-40786-5_4

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