Abstract
This chapter presents several techniques to achieve high-performance and/or low-energy operation of DML circuits. We introduce several optimization methodologies for DML circuits while focusing on gate-level techniques. This goal is primarily achieved by utilizing the logical effort model (LE) which was uniquely adapted to DML. We discuss several approaches which trade off the accuracy of the solution with simplicity and complexity (i.e., the complete and approximate LE models). The method is then generalized to complex gates and branches. Finally, we compare and evaluate the methods discussed.
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Notes
- 1.
Note that DML’s dual-mode methodology can be applied over other static-logic families, e.g., PTL and not only CMOS; however, in this case the DML-LE approach in this chapter would not apply directly.
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Levi, I., Fish, A. (2021). Optimization of DML Gates. In: Dual Mode Logic. Springer, Cham. https://doi.org/10.1007/978-3-030-40786-5_3
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DOI: https://doi.org/10.1007/978-3-030-40786-5_3
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