Abstract
This chapter discusses the concept behind DML. It presents DML basic architectures at the circuit level and describes the two modes of DML operation in detail. Specifically, it elaborates on the range of device-level topologies to construct a DML gate and the valid DML gate-level combinations. This is followed by a short discussion on the rationales, advantages, and disadvantages of each topology, as well as DML in general. In this chapter, we mainly focus on speed (performance) and energy consumption as evaluation metrics and compare DML designs to standard CMOS designs.
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Levi, I., Fish, A. (2021). Introduction to Dual Mode Logic (DML). In: Dual Mode Logic. Springer, Cham. https://doi.org/10.1007/978-3-030-40786-5_2
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DOI: https://doi.org/10.1007/978-3-030-40786-5_2
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