Abstract
Processing steps to integrate active and passive components in a CMOS-based technology are discussed in this chapter. A basic description of unit processes is first presented. An overview of a baseline CMOS process is then given, followed by a discussion of process modules that are added to the baseline process to fabricate components for mixed-signal (MS) and radio-frequency (RF) CMOS, analog CMOS, high-speed BiCMOS, and Bipolar-CMOS-DMOS (BCD). Illustrative cross-sectional views of the numerous analog component constructions are provided.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
B. El-Kareh, Fundamentals of Semiconductor Processing Technologies, Second Printing. (Kluwer Academic Publishers, Boston, 1997)
S. Wolf, R. Taber, Silicon Processing for the VLSI Era (Lattice Press, Sunset Beach, CA, 1999)
Z.J. Ma, J.C. Chen, Z.H. Liu, J.T. Krick, Y.C. Cheng, C. Hu, P.K. Ko, Suppression of boron penetration in p+ polysilicon gate P-MOSFET using low-temperature gate-oxide N2O anneal. IEEE Elec. Dev. Letters 15(3), 109–111 (1994)
M. Marin, J.C. Vildeuil, B. Tavel, B. Duriez, F. Arnaud, P. Stolk, M. Woo, Can 1/f noise in MOSFETs be reduced by gate oxide and channel implantation? AIP Conf. Proc. 780, 195–198 (2005)
Y.K. Choi, I.Y. Park, H.C. Lim, M.Y. Kim, C.J. Yoon, N.J. Kim, K.D. Yoo, L.N. Hutter, A versatile 30V analog CMOS process in a 0.18μm technology for power management applications. ISPSD Proceedings 219–222 (2011)
M.T. Bohr, Interconnect scaling – the real limiter to high performance ULSI. IEEE IEDM Tech. Digest 241–244 (1995)
P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S. H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, M. Bohr, A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57μm2 SRAM cell. IEEE IEDM Tech. Digest, pp. 657–660 (2004)
C. Ryu, K.W. Kwon, A.L.S. Loke, H.B. Lee, T. Nogonami, V.M. Dubin, R.A. Kavari, G.W. Ray, S.S. Wong, Microstructure and reliability of copper interconnects. IEEE Trans. Electron Dev. 46(6), 1113–1120 (1999)
E. P. Barth, T. H. Ivers, P. S. McLaughlin, A. McDonald, E. N. Lenine, S. E. Greco, J. Fitzsimmons, I. Melville, T. Spooner, C. DeWan, X. Vhen, D. Manger, H. Nye, V. McGahay, G. H. Biery, R. D. Goldblatt, T. C. Chen, Integration of copper and fluorinated glass for 0.18μm interconnections. IEEE IITC, pp. 219–221 (2000)
C.W. Kaanta, S. G. Bombardier, W. J. Cote, W. R. Hill, G. Kerszykowski, H. S. Landis, D. J. Poindexter, C. W. Pollard, G. H. Ross, J. G. Ryan, S. Wolff, J. E. Cronin, Dual damascene: a ULSI wiring technology. Proceedings VLSI Multilevel Interconnection Conference, pp. 144–152 (1991)
T.A. Tran, L. Yong, B. Williams, S. Chen, A. Chen, Fine pitch probing, wirebonding and reliability of aluminum capped copper bond pads. Int. J. Microcircuits and Electr. Pack. 23(3), 332–338 (2000)
D. Buss, B.L. Evans, J. Bellay, W. Krenik, B. Haroun, D. Leipold, K. Maggio, J.Y. Yamg, T. Moise, SOC CMOS technology for personal internet products. IEEE Trans. Electron Dev. 50(3), 546–556 (2003)
R. Aparicio, A. Hajimiri, Capacity limits and matching properties of integrated capacitors. J. Solid-State Circuits 37(3), 384–393 (2002)
M. Armacost, A. Augustin, P. Felsner, Y. Feng, G. Friese, J. Heidenreich, G. Hueckel, O. Prigge, K. Stein, A high reliability metal insulator metal capacitor for 0.18 μm copper technology. IEEE IEDM Tech. Digest 157–160 (2000)
R. Liu, C-Y Lin, E. Harris, S. Merchant, S.W. Downey, G. Weber, N.A. Ciampa, W. Tai, W.Y.C. Lai, M.D. Morris, J.E. Bower, J.F. Miner, J. Frackoviak, W. Mansfield, D. Barr, R. Keller, C-P Chang, C-S Pai, S.N. Rogers, R. Gregor, Single mask metal-insulator-metal (MIM) capacitor with copper damascene metallization for sub-0.18 μm mixed-mode signal and system-on-a-chip (SOC) applications. International Interconnect Tech. Conference, pp. 111–113 (2000)
Z. Chen, K.M. Lin, C.C. Kuo, T.C. Ko, J.C. Huang, J.P. Wang, Y.F. Lin, T.W. Wu, T.C. Su, C.C. Liao, M.C. Jeng, Fabrication and integration of high performance mixed signal and RF passive components in 0.13 μm Cu BEOL technologies. International Conference on Solid-State and Integrated Circuits Technology, pp. 175–178 (2004)
R. Mahnkopf, K-H. Allers, M. Armacost, A. Augustin, J. Barth, G. Brase, R. Busch, E. Demm, G. Dietz, B. Flietner, G. Friese, F. Grellner, K. Han, R. Hannon, H. Ho, M. Hoinkis, K. Holloway, T. Hook, S. Iyer, P. Kim, G. Knoblinger, B. Lemaitre, C. Lin, R. Mih, W. Neumueller, J. Pape, O. Prigge, N. Robson, N. Rovedo, T. Schafbauer, T. Schimi, K. Schruefer, S. Srinivasan, M. Stetter, F. Towler, P. Wensley, C. Wann, R. Wong, R. Zoeller, B. Chen, ‘System on a chip’ technology platform for 0.18 μm digital, mixed signal & eDRAM applications. IEEE IEDM Tech. Digest, pp. 849–852 (1999)
P. Zurcher, P. Alluri, P. Chu, A. Duvallet, C. Happ, R. Henderson, J. Mendonca, M. Kim, M. Petras, M. Raymond, T. Remmel, D. Roberts, B. Steimle, J. Stipanuk, S. Straub, T. Sparks, M. Tarabbia, H. Thibieroz, M. Miller, Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies. IEEE IEDM Tech. Digest, pp. 153–156 (2000)
C.H. Ng, C.-S. Ho, S.-F.S. Chu, S.-C. Sun, MIM capacitor integration for mixed-signal/RF applications. IEEE Trans. Electron Dev. 52(97), 1399–1409 (2005)
P.-Y. Chiu, M.-D. Ker, Metal-layer capacitors in the 65nm CMOS process and the application for low-leakage power-rail ESD clamp circuit. Microelectron. Reliab. 54, 64–70 (2014)
J.S. Dunn, D.C. Ahlgren, D.D. Coolbaugh, N.B. Feilchenfeld, G. Freeman, D.R. Greenberg, E.A. Groves, F.J. Guarin, Y. Hammad, A.J. Joseph, L.D. Lanzerotti, S.A.S. Onge, B.A. Orner, J.S. Rieh, K.J. Stein, S.H. Voldman, P.C. Wang, M.J. Zierak, S. Subbanna, D.L. Harame, D.A. Herman, B.S. Meyerson, Foundation of rf CMOS and SiGe BiCMOS technologies. IBM J. Res. Dev. 47(2/3), 101–138 (2003)
B. El-Kareh, Silicon Devices and Process Integration (Springer, New York, 2009), p. 451
I.C. Kizilyalli, F.A. Stevie, J.D. Bude, N+-polysilicon gate PMOSFETs with indium doped buried-channels. IEEE Electron Dev. Lett. 17(2), 46–49 (1996)
G. Guegan, S. Deleonibus, C. Caillat, S. Tedesco, B. Dal’zotto, M. Heitzmann, M.E. Nier, P. Mur, A 0.10 μm buried p-channel MOSFET with through the gate boron implantation and arsenic tilted halo. Solid State Electron. 46(3), 343–348 (2002)
Y.C. Kwon, H.C. Seol, S.K. Hong, O.K. Kwon, Process optimization of integrated SiCr thin-film resistor for high-performance analog circuits. IEEE Trans. Electron. Dev. 61(1), 8–14 (2014)
J. Ramirez-Angulo, R. Geiger, New laser-trimmed resistor structures for very high stability requirements. IEEE Trans. Electron. Dev. 35(4)., part 2,), 516–518 (1988)
Y.K. Choi, I. Y. Park, H. S. Oh, W. Lee, N. J. Kim, K. D. Yoo, Implementation of low Vgs (1.8V) 12V RF-LDMOS for high-frequency DC-DC converter applications. ISPSD Proceedings, pp. 125–128 (2012)
C. Bulucea, S.R. Bahl, W.D. French, J.J. Yang, P. Francis, T. Harjono, V. Krishnamurthy, J. Tao, C. Parkerl, Physics, technology, and modeling of complementary asymmetric MOSFETs. IEEE Trans. Electron Dev. 57(10), 2363–2380 (2010)
Author information
Authors and Affiliations
Problems
Problems
The temperature is 25 °C unless otherwise stated.
-
1.
Describe a process with one polysilicon level and eight copper metal levels to fabricate the following components: LV-CMOS, HV-CMOS, isolated CMOS, DECMOS, LFC, NPN, and inductor. Assume existing metal levels are used for the inductor.
-
2.
The four identical NMOS devices in the figure below must be isolated from substrate without changing their layout. Show a top view and cross-sectional view for how this can be done while minimizing the overall area consumed. Discuss your assumptions.
-
3.
For an isolated native NMOSFET with a substrate concentration of 1015 cm−3 and a maximum drain voltage of 5.5 V:
-
(a)
Show a top- and cross-sectional view.
-
(b)
Estimate the minimum channel length to avoid punch-through between source and drain.
-
(c)
Estimate the minimum distance between drain and underlying N-region required to avoid punch-through between the two regions.
Assume a step junction in both cases and ND = 5 × 1017 cm−3 in the deep N-region.
-
(a)
-
4.
The figure below describes via etching to both plates of a MIM capacitor with oxide as the dielectric. Determine the minimum capacitor top-plate thickness under the following conditions: (a) IMD thickness = 1 μm, (b) capacitor density = 1 fF/μm2, (c) a 10% via over-etch of IMD is done, (d) the IMD to top-plate metal selectivity is 25:1, and (e) the etched thickness of the top-plate metal must be <25% of the original top-plate thickness.
-
5.
Assume that the LDD of an NMOSFET with a rectangular polysilicon gate is implanted in a “4-way rotation” mode at an angle of 45° immediately after growing a 10-nm sidewall oxide, using resist as a mask. For a resist thickness of 800 nm, estimate the minimum space between resist edge and poly-edge required to avoid “shadowing,” and ensure that the implanted dopants reach their maximum penetration and dose under the polysilicon. Assume that both the resist and poly-edges are vertical.
-
6.
Consider an N+-polysilicon resistor placed on STI. A voltage of +5 V is applied to the resistor with respect to the underlying P-type substrate at ground.
-
(a)
Describe qualitatively how the resistor to substrate capacitance changes when a floating N-well is placed under the STI.
-
(b)
Estimate this change for an STI oxide thickness of 0.4 μm, a uniform N-well concentration of 1017 cm−3, and a uniform substrate concentration of NA = 1015 cm−3.
-
(a)
-
7.
Estimate the minimum drawn NBL to NBL spacing required to achieve a 50 V punch-through voltage between two NBL regions shown in the figure below. Assume an epi thickness of 8 μm, a degenerately doped NBL with 1.7 μm lateral diffusion, NA = 1015 cm−3 in both epi and substrate, and planar NBL sidewalls (do not use cylindrical coordinates).
-
8.
For a BCD epitaxy process using NBL, calculate the minimum epi thickness needed to achieve a 50 V avalanche breakdown voltage between P-body and NBL under the following conditions: P-body junction depth, xj = 1.5 μm; NBL up-diffusion into epi, 2 μm; and P-epi concentration, ND = 1 × 1015 cm−3. Assume uniform P-body concentration NA = 5 × 1017 cm−3 and degenerately doped NBL.
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
El-Kareh, B., Hutter, L.N. (2020). Process Integration. In: Silicon Analog Components. Springer, Cham. https://doi.org/10.1007/978-3-030-15085-3_9
Download citation
DOI: https://doi.org/10.1007/978-3-030-15085-3_9
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-15084-6
Online ISBN: 978-3-030-15085-3
eBook Packages: EngineeringEngineering (R0)