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Analog/RF CMOS

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Silicon Analog Components

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Abstract

The trade-offs between parameters are different for digital, analog, and RF CMOS. In particular, there are conflicting requirements between analog and digital CMOS on operating voltage level, reduced low-frequency noise, high output resistance, low component mismatch, and high linearity. Thus, modifications must be made to the basic digital structure to satisfy analog circuit needs. In contrast, the characteristics of RF CMOS are essentially the same as those of high-speed digital CMOS so that both designs can be integrated on the same chip with little added complexity. In this chapter we first review the characteristics of the two-terminal MOS structure. This lays the groundwork for the discussion of MOSFET and CMOS characteristics in the sections that follow, with emphasis on key analog parameters. The chapter concludes with a review of mobility enhancement techniques, high-κ dielectrics, FinFETs, and fully depleted SOI MOSFETs and a brief discussion of analog CMOS applications.

The terms MOS, MOSFET, and CMOS stand for metal–oxide–silicon, MOS field-effect transistor, and complementary MOS (transistors). In earlier technologies, the metal of choice was aluminum, the insulator (dielectric) was silicon dioxide (or simply, oxide), and the semiconductor was silicon. The term MOS is still used, even for structures having a conductor other than metal, an insulator other than oxide, and a semiconductor material other than silicon.

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Notes

  1. 1.

    The subscripts “s” and “b” will be used throughout the chapter to indicate, respectively, surface and bulk parameters.

  2. 2.

    Unless otherwise stated, E, EF, Ei, EC, EV, and Eg are energies expressed in eV; ϕ, ψ, and χ are expressed as potentials in V. Energies and potentials have the same numerical value but different units. Example, kT is expressed in eV and kT/q in V.

  3. 3.

    The values in the plot are extracted from the International technology Roadmap for Semiconductors, ITRS updates (www.itrs.net). The DRAM half-pitch is a metric for “Technology Generation.”

  4. 4.

    LOCOS stands for Local Oxidation of Silicon and is further discussed in Chap. 9.

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Authors and Affiliations

  1. PIYE, Cedar Park, TX, USA

    Badih El-Kareh

  2. Lou Hutter Consulting, Dallas, TX, USA

    Lou N. Hutter

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Problems

Problems

  1. 1.

    An MOS structure formed on P-type substrate is biased in strong accumulation. Assume that the maximum field in the oxide may not exceed 5.5 × 106 V/cm and estimate the maximum excess holes/cm2 that can be induced in silicon. Assume an oxide thickness of 7.2 nm and find the maximum voltage that may be applied to the gate.

  2. 2.

    For the MOS structure in Problem 1, find the surface potential that yields a concentration of holes at the surface of 1020 cm−3 at 25 °C. What is the surface concentration of electrons for this case?

  3. 3.

    An idealized MOS structure is constructed on a P-type substrate of uniform concentration NA = 5 × 1016 cm−3.

    1. (a)

      Assume an oxide thickness tox = 12.5 nm and 25 °C and find the threshold voltage.

    2. (b)

      While the MOS structure is kept at 25 °C in a dark enclosure, the gate voltage is pulsed from 0 to +5 V and held constant at +5 V. Find the depletion width immediately after the pulse.

    3. (c)

      Estimate the inversion layer concentration, Qn, after the surface fully relaxes to its steady-state condition.

  4. 4.

    Show that for a uniformly doped MOSFET body the body-bias effect can be expressed as

    $$ \frac{\mathrm{d}{V}_{\mathrm{T}}}{\mathrm{d}{V}_{\mathrm{B}}}=\frac{C_{\mathrm{min}}}{C_{\mathrm{max}}-{C}_{\mathrm{min}}} $$

    where VB is the source-to-body voltage.

  5. 5.

    Approximate the field at the silicon surface field and in the oxide for the structure in Problem 3. For

    1. (a)

      VG = VT at onset of strong inversion.

    2. (b)

      VG = 5 V, in deep depletion.

    3. (c)

      VG = 5 V in steady-state strong inversion.

  6. 6.

    The following assumptions are made for simplicity: Long and wide buried-channel PMOS; uniform buried-channel concentration NA = 5 × 1016 cm−3; buried-channel junction depth xjbp = 0.12 μm; N-well concentration at junction ND = 5 × 1016 cm−3; EOT teq = 12.5 nm; degenerately doped N+-poly gate; temperature 25 °C. Estimate: The threshold voltage and subthreshold slope.

  7. 7.

    An NMOS having an EOT of 13 nm is fabricated on a 2 Ω-cm substrate. The source, drain, and substrate are grounded and the gate biased such that the substrate surface potential is +0.5 V. Assume 25 °C, Qeff = 0 and find the surface concentrations of electrons and holes. For an N+-polysilicon gate, find the corresponding gate voltage.

  8. 8.

    For the structure in Problem 6, find the surface potential at onset of strong inversion, the maximum depletion width, the maximum bulk charge density in steady-state strong inversion, the threshold voltage, and the number of electrons per cm2.

  9. 9.

    An NMOS is made on a P-type substrate with NA = 2.5 × 1017 cm−3, inversion teq = 8.0 nm, and an N+-polysilicon gate. The effective oxide charge is Qeff = +2 × 1011q C/cm2. The effective channel dimensions are Leff = 0.5 μm, Weff = 2 μm. For 25 and 140 °C find:

    1. (a)

      The threshold voltage for VD = 0.1 V.

    2. (b)

      The subthreshold slope in mV/decade.

    3. (c)

      The drain current at (VG − VT) = 3.0 V, VD = 0.1 V and 3.0 V.

    4. (d)

      The transconductance for the voltage conditions in (c).

  10. 10.

    A long- and wide-channel isolated NMOS having a P-well concentration NA = 1.8 × 1017 cm−3, teq = 13.0 nm in inversion. Assume 25 °C. By how much should the source to P-well junction be reverse biased to obtain an increase in VT of 0.2 V?

  11. 11.

    Assume that the channel length in Problem 8. Is Leff = 1 μm and neglect fringe capacitances. Estimate fT at 25 °C for VG − VT = 3.0 V and VD = 3.0 V.

  12. 12.

    A 5 V PMOS is biased at (VG − VT) = −2.5 V. The drain current is measured as 0.251 mA/μm (width) at VD = −3 V and 0.252 mA/μm at VD = −4 V. Find the drain conductance, the output resistance and the Early voltage.

  13. 13.

    The threshold voltage of an enhancement-mode NMOS is 0.6 V. Find the dose of arsenic that must be implanted in silicon under the gate of the NMOS to transform it into a depletion-mode NMOS with VT = −0.8 V. Assume teq = 13 nm and the implanted arsenic to have a fully ionized impulse profile located at the silicon surface.

  14. 14.

    The gate, source, and drain of a PMOS are degenerately doped, and the gate oxide thickness is 12.5 nm. Approximate the field in the oxide in the overlapped drain region for the following cases:

    1. (a)

      The drain is at ground and the gate is P+-poly at 5 V.

    2. (b)

      The drain is at ground and the gate is N+-poly at 5 V.

    3. (c)

      The gate is P+-poly at ground and the drain is at 5 V.

    4. (d)

      The gate is N+-poly at ground and the drain is at 5 V.

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El-Kareh, B., Hutter, L.N. (2020). Analog/RF CMOS. In: Silicon Analog Components. Springer, Cham. https://doi.org/10.1007/978-3-030-15085-3_6

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