PN Junctions

El-Kareh, Badih; Hutter, Lou N.

doi:10.1007/978-3-030-15085-3_3

Badih El-Kareh³ &
Lou N. Hutter⁴

1096 Accesses

Abstract

The PN junction is the fundamental building block of most silicon devices. The junction shape, doping profile, and characteristics have a direct impact on device and circuit performance. The chapter begins with a basic description of junction types and their thermal equilibrium characteristics. This is followed by a review of junction forward-bias characteristics under low-level and high-level injection and reverse-biased characteristics under low- and high-field conditions. The junction switching behavior and reverse recovery time are then described, followed by examples of stand-alone junction applications.

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Notes

1.
Doping techniques and other processing steps are described in “Fundamentals of Semiconductors Processing Technologies,” by B. El-Kareh, Kluwer Academic Publishers, Boston, 1995.
2.
Unless otherwise stated, C denotes capacitance per cm².
3.
At very high frequencies, the distributed series resistances and capacitances (RC components) can impact the frequency response of the junction. As a rule of thumb, the signal frequency should be smaller than RC. Note that RC has the unit time, t: R = V/I, I = Q/t, C = Q/V, RC = t.
4.
The term Zener breakdown is used to describe a breakdown mechanism caused by tunneling to distinguish it from avalanche breakdown. This may cause some confusion. The error stems from misinterpreted initial breakdown measurements.

References

R.W. Dutton, Z. Yu, C.A.D. Technology, Computer Simulation of IC Process and Devices (Kluwer Academic Publishers, 1993)
Google Scholar
S.M. Sze, G. Gibbons, Effect of junction curvature on breakdown voltages in semiconductors. Solid State Electron. 9(9), 831–845 (1966)
Article Google Scholar
W. Shockley, W.T. Read, Statistics of recombination of holes and electrons. Phys. Rev. 87(5), 835–842 (1952)
Article Google Scholar
R.N. Hall, Electron-hole recombination in Germanium. Phys. Rev. 87(2), 387–387 (1952)
Article Google Scholar
A.S. Grove, Physics and Technology of Semiconductor Devices (Wiley, 1967)
Google Scholar
C.R. Crowell, S.M. Sze, Temperature dependence of avalanche multiplication in semiconductors. Appl. Phys. Lett. 9(6), 242–244 (1966)
Article Google Scholar
J. Baliga, Fundamentals of Power Semiconductor Devices (Springer, 2008), p. 100
Google Scholar
C. Zener, A theory of electrical breakdown voltages of solid dielectrics. Proc. Roy. Soc. London A145, 523–529 (1934)
Article Google Scholar
A.E. Garside, P. Harvey, The characteristics of silicon voltage-reference diodes. IET 106(7), 982–990 (1959)
Google Scholar
P.E. Gray, D. DeWitt, A.R. Boothroyd, J.F. Gibbons, SEEC, in Physical Electronics and Circuit Models of Transistors, vol. 2, (Wiley, 1964)
Google Scholar
A.B. Phillips, Transistor Engineering (McGraw-Hill, 1962)
Google Scholar
R.C. Dobkin, Monolithic temperature stabilized voltage reference with 0.5 ppm/°C drift. IEEE ISSCC, 108–109 (1976)
Google Scholar
B. Reich, J. Erickson, Zener diodes as vehicular and aircraft transient suppressors. IEEE AES 6(4), 498–502 (1970)
Google Scholar
R.W. Gurtler, Avalanche drift instability in planar passivated p-n junctions. IEEE Trans. Electron Dev., ED 13(12), 980–986 (1968)
Article Google Scholar
W.L. Guo, R.S.S. Huang, L.Z. Zheng, Y.C. Song, Walkout in p-n junctions including charge trapping saturation. IEEE Trans. Electron Dev. 34(8), 1788–1794 (1987)
Article Google Scholar
J.F. Verwey, A. Hering, R. De Wendt, W.V.D. Hofstad, Drift of the breakdown voltage in p-n junction in silicon (walkout). Solid State Electron. 20(8), 689–695 (1977)
Article Google Scholar
K.C. Saraswat, J.D. Meindl, Breakdown walkout in planar p-n junctions. Solid State Electron. 21(6), 813–819 (1978)
Article Google Scholar
J.F. Verwey, Hole currents in thermally grown SiO₂. J. Appl. Phys. 43(5), 2273–2277 (1972)
Article Google Scholar
A. Ito, M.D. Church, C.S. Rhee, J.M. Johnson, J.T. Gasner, W.A. Ligon, P.A. Begley, G.A. DeJong, A fully complementary BiCMOS technology for 10 V mixed-signal circuit applications. IEEE Trans Electron Dev. 41(7), 1149–1160 (1994)
Article Google Scholar
R.B. Fair, H.W. Wivell, Zener and avalanche breakdown in as-implanted low-voltage Si n-p junctions. IEEE Trans. Electron. Dev., ED 23(5), 512–518 (1976)
Article Google Scholar
P.C. Todd, Snubber Circuits: Theory, Design and Applications, Application Note (Unitrode Corp., 1993)
Google Scholar
W. Doherty, PIN Diode Fundamentals, MicroNotes, Series 701 (Microsemi Corp, Watertown, 2006)
Google Scholar
M. Kyomasu, Development of an integrated high speed silicon PIN photodiode sensor. IEEE Trans. Electron Dev. 42(6), 1093–1099 (1995)
Article Google Scholar

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Authors and Affiliations

PIYE, Cedar Park, TX, USA
Badih El-Kareh
Lou Hutter Consulting, Dallas, TX, USA
Lou N. Hutter

Authors

Badih El-Kareh
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Problems

1.
In a step junction, N_D = 10¹⁸ cm⁻³ and N_A = 10¹⁶ cm⁻³. Find for thermal equilibrium at 25 and 85 °C:
1. (a)
  The built-in voltage
2. (b)
  The depletion widths x_dp and x_dn
3. (c)
  The total positive charge per cm²
4. (d)
  The peak field
5. (e)
  The planar capacitance per cm²
2.
One special case of a nonuniform profile is shown in the figure below. It is characterized by a concentration gradient a where the impurity concentration changes linearly as N_D − N_A = ax. Assume the depletion approximation, a = 5 × 10²¹ cm⁻⁴, and thermal equilibrium at 25 °C.
Fig. P2
Idealized linearly graded approximation
Full size image
1. (a)
  Plot the electrical field as a function of depleted width.
2. (b)
  Plot the electrostatic potential as a function of depleted width. Hint: Use (3.5).
3. (c)
  Find the built-in voltage, V_bi. The built-in voltage cannot be extracted analytically. Instead, the following equation can be solved iteratively:
  $$ {V}_{\mathrm{b}\mathrm{i}}=\frac{2 kT}{3q}\ln \frac{3{\varepsilon}_0{\varepsilon}_{\mathrm{Si}}{a}^2{V}_{\mathrm{b}}}{2{qn}_{\mathrm{i}}^3} $$
4. (d)
  Find the total thermal equilibrium depletion width.
3.
Consider a PN junction with uniform N_D on the N-side and N_A on the P-side and narrow widths W_n, W_p as shown in Fig. 3.14. The ratio of thermal equilibrium electron concentration $ {\overline{n}}_{\mathrm{p}} $ at the boundary of the depletion layer on the P-side to the electron concentration $ {\overline{n}}_{\mathrm{n}} $ at the depletion boundary of the N-side, and the corresponding relation for holes are given by (3.7).
1. (a)
  Assume that when a forward voltage V_F is applied to the junction, the barrier is reduced by V_F and the relations for electrons follow Boltzmann’s distribution law as
  $$ {n}_{\mathrm{p}}={n}_{\mathrm{n}}{\mathrm{e}}^{-q\left({V}_{\mathrm{bi}}-{V}_{\mathrm{F}}\right)/ kT};\kern1em {p}_{\mathrm{n}}={p}_{\mathrm{p}}{\mathrm{e}}^{-q\left({V}_{\mathrm{bi}}-{V}_{\mathrm{F}}\right)/ kT} $$
  
  Use the results to show that
  $$ \Delta {n}_{\mathrm{p}}={\overline{n}}_{\mathrm{p}}\left({\mathrm{e}}^{qV_{\mathrm{F}}/ kT}-1\right);\kern1em \Delta {p}_{\mathrm{n}}={\overline{p}}_{\mathrm{n}}\left({\mathrm{e}}^{qV_{\mathrm{F}}/ kT}-1\right) $$
2. (b)
  Assume that the injected excess minority-carrier concentration drops linearly from the depletion edge to the contacts and derive (3.25a and 3.25b).
4.
A PN junction is made in a 2 Ω-cm resistivity silicon P-type wafer by implanting and diffusing arsenic at the surface such that the N-type region has a concentration of 10²⁰ cm⁻³. The area of the junction is 100 × 100 μm². The thickness of the wafer is 750 μm. The trap density in the P-type wafer is N_T = 10¹² cm⁻³. Ohmic contacts are made to the N-region and bottom of the wafer. At 25 °C, determine
1. (a)
  The thermal equilibrium built-in voltage
2. (b)
  The reverse current for a reverse voltage V_R = 5 V
3. (c)
  The forward current for a forward voltage V_F = 0.5 V
4. (d)
  The junction capacitance at a reverse voltage V_R = 5 V
5. (e)
  The reverse voltage necessary to spread the depletion region 25 μm in the P-region
6. (f)
  The junction breakdown voltage
5.
The concentrations in an abrupt PN junction are N_A = N_D = 5 × 10¹⁸ cm⁻³. At what reverse voltage will this junction breakdown. Assume that Zener breakdown occurs when the peak field reaches 10⁶ V/cm.
6.
Consider the N⁺P junction in the figure below. The N⁺-layer is externally shorted to the P⁺ substrate contact. Impact ionization in an adjacent circuit generates a hole current that passes under the N⁺-region and is collected at the substrate contact. The resistance between point A in the substrate immediately under the N⁺-region and the P⁺-contact is about 4 kΩ. The average trap density in the substrate is 10¹² cm⁻³, and the wafer temperature is 25 °C.
1. (a)
  At what substrate current I_sub will the N⁺P junction develop a forward bias of 0.25 V?
2. (b)
  For a forward bias of 0.25 V, what is the excess electron concentration at the depletion boundary in the substrate?
3. (c)
  Estimate the diffusion length minority electrons in the substrate.
7.
Consider a one-sided N⁺P step junction having a junction depth of 0.3 μm and a uniform background concentration N_A = 10¹⁷ cm⁻³. The effective density of generation–recombination sites in the P-region is 10¹⁰ cm⁻³. An N⁺-region is placed 0.8 μm below the silicon surface and reverse-biased at 5 V.
1. (a)
  Calculate the electron current density for a forward-biased voltage of 0.8 V at 25 and 100 °C.
2. (b)
  Punch-through occurs when the depletion regions of the top and bottom junction merge in the P-region. The reverse voltage is increased until a current of 1 μA/μm² is measured. Is the main mechanism for this current impact ionization, punch-through, or thermal generation?
8.
A one-sided N⁺P junction is formed by diffusing a heavily doped N-region to a depth of 0.5 μm into a 10 Ω-cm P-substrate of thickness 725 μm. The density of recombination–generation sites in the P-region is 5 × 10¹¹ cm⁻³. A forward-biased V_F = 0.7 V is applied to the junction at 25 °C. Will the minority-carrier electrons reach the backside of the substrate?
9.
An abrupt N⁺P junction is formed by implanting and diffusing arsenic through a 2 × 2 μm² mask opening into a P-type substrate. The metallurgical junction is 0.25 μm deep, and the substrate is uniformly doped with boron at a concentration of 10¹⁷ cm⁻³. Assume cylindrical junction edges and compare the breakdown voltage at the edge to that in the planar part of the junction at 25 °C.
10.
The intrinsic region in a PIN junction is 1 μm thick. Assume that the N-region and P-region are heavily doped. For a reverse voltage, V_R = 5 V and 25 °C, calculate
1. (a)
  The junction capacitance
2. (b)
  The electric field in the intrinsic region
3. (c)
  The transit time for an electron–hole pair generated by a photon at the center of the intrinsic region