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Mismatch and Noise

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Silicon Analog Components

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Abstract

Component mismatch limits the precision of analog circuits, such as converters and current mirrors, and noise ultimately sets a lower limit on signals that can be detected and processed. Both mismatch and noise can have a large impact on the precision of analog and mixed-signal circuits. The first part of this chapter discusses random and systematic mismatch in passive and active components, mismatch characterization, and process and design methods to reduce mismatch. The second part describes the different noise mechanisms, focusing on low-frequency noise and methods to reduce it.

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Authors and Affiliations

  1. PIYE, Cedar Park, TX, USA

    Badih El-Kareh

  2. Lou Hutter Consulting, Dallas, TX, USA

    Lou N. Hutter

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Problems

Problems

The temperature is 300 K unless otherwise stated.

  1. 1.

    An NMOS pair exhibits a standard deviation of threshold voltage mismatch, \( {\sigma}_{\Delta {V}_{\mathrm{T}}}, \) of 10 mV. Scattering of phosphorus during implantation causes the effective doping concentration in the channel of one NMOS to increase by 1010 cm−2, while the other NMOS remains unaffected. Assume a long and wide channel and an equivalent oxide thickness of 12.5 nm and sketch the distribution of a large number of mismatch measurements.

  2. 2.

    The figure below shows two N-well resistors that are identically constructed in a P-substrate, except for a degenerately doped poly conductor crossing one of the resistors. Assume a uniform N-well phosphorus concentration of 5 × 1016 cm−3, a uniform P-substrate boron concentration of 5 × 1014 cm−3, and disregard edge effects. Estimate the systematic mismatch between the two resistors (Fig. P2).

    Fig. P2
    figure 32

    N-well resistor matching problem 5.2

    Full size image
  3. 3.

    Two identical MOSFETs are connected with first metal and operated in the linear mode. The metal line connecting the common source to ground is 50 μm long and 10 μm wide, and the metal lines connecting the MOSFET drains are 50 μm long and 20 μm wide on one MOSFET and 50 μm long and 0.25 μm wide on the other. Describe qualitatively how this design would affect mismatch.

  4. 4.

    Consider the array of polysilicon resistors of a uniform sheet resistance 250 Ω/□ in Fig. P4. The resistor-body length body is L = 10 μm and its drawn width and space, respectively, W = 0.5 μm and S = 0.5 μm. The measured resistance is 6250 Ω at each end of the array and 5000 Ω at the array center. Assume the difference to be solely due to a linear gradient in over-etch, and

    1. (a)

      Find the etch-bias per resistor edge.

    2. (b)

      Plot the systematic mismatch as a function of distance between array center and array edge.

    Fig. P4
    figure 33

    Polysilicon resistor matching Problem 5.4

    Full size image
  5. 5.

    Calculate the shot noise in a diode current of 1.5 mA in a bandwidth of 1 MHz.

  6. 6.

    The power spectral density of the noise voltage is measured as 2.5 × 10−16 V2/Hz for a bandwidth of 1 MHz. Find the root-mean-square of the noise voltage.

  7. 7.

    A polysilicon resistor has a resistance of 250 Ω. What is the PSD of the thermal noise voltage 300 K?

  8. 8.

    The resistor in Problem 5.6 shows a flicker noise PSD of 3.2 × 10−19 A2/Hz. Find the root-mean-square of current noise in the bandwidth 10 Hz–1 kHz.

  9. 9.

    The flicker noise is measured on an NMOSFET as \( {S}_{I_{\mathrm{D}}} \) = 5 × 10−17 A2/Hz at 100 Hz, VG − VT = 2.5 V, and ID = 5 mA. The channel length and width are, respectively, 0.6 and 10 μm. For an equivalent oxide thickness teq = 12.5 nm, estimate the effective oxide trap density and the input-referred voltage noise.

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El-Kareh, B., Hutter, L.N. (2020). Mismatch and Noise. In: Silicon Analog Components. Springer, Cham. https://doi.org/10.1007/978-3-030-15085-3_10

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