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Convolutional turbo codes

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Codes and Turbo Codes

Part of the book series: Collection IRIS ((IRIS))

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Abstract

The error correction capability of a convolutional code increases when the length of the encoding register increases. This is shown in Figure 7.1, which provides the performance of four RSC codes with respective memories ? = 2, 4, 6 and 8, for rates 1/2, 2/3, 3/4 and 4/5, decoded according to the MAP algorithm. For each of the rates, the error correction capability improves with the increase in ?, above a certain signal to noise ratio that we can assimilate almost perfectly with the theoretical limit calculated in Chapter 3 and identified here by an arrow. To satisfy the most common applications of channel coding, a memory of the order of 30 or 40 would be necessary (from a certain length of register and for a coding rate 1/2, the minimum Hamming distance of a convolutional code with memory ? is of the order of ?). If we knew how to easily decode a convolutional code with over a billion states, we would no longer speak much about channel coding and this book would not exist.

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Editors and Affiliations

  1. Télécom Bretagne, CS 83818, 29238, Brest Cedex 3, France

    Claude Berrou

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(2010). Convolutional turbo codes. In: Berrou, C. (eds) Codes and Turbo Codes. Collection IRIS. Springer, Paris. https://doi.org/10.1007/978-2-8178-0039-4_7

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  • DOI: https://doi.org/10.1007/978-2-8178-0039-4_7

  • Publisher Name: Springer, Paris

  • Print ISBN: 978-2-8178-0038-7

  • Online ISBN: 978-2-8178-0039-4

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