Abstract
We present recent results of a performance benchmark of selected low-level vision algorithms implemented on different high-speed embedded platforms. The algorithms were implemented on a digital signal processor (DSP) (Texas Instruments TMS320C6414), a field-programmable gate array (FPGA) (Altera Stratix-I and II families) as well as on a mobile PC processor (Intel Mobile Core 2 Duo T7200). These implementations are evaluated, compared, and discussed in detail. The DSP and the mobile PC implementations, both making heavy use of processor-specific acceleration techniques (intrinsics and resource optimized slicing direct memory access on DSPs or Intel integrated performance primitives Library on mobile PC processors), outperform the FPGA implementations, but at the cost of spending all its resources to these tasks. FPGAs, however, are very well suited to algorithms that benefit from parallel execution.
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Baumgartner, D., Roessler, P., Kubinger, W., Zinner, C., Ambrosch, K. (2009). Benchmarks of Low-Level Vision Algorithms for DSP, FPGA, and Mobile PC Processors. In: Kisačanin, B., Bhattacharyya, S.S., Chai, S. (eds) Embedded Computer Vision. Advances in Computer Vision and Pattern Recognition. Springer, London. https://doi.org/10.1007/978-1-84800-304-0_5
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DOI: https://doi.org/10.1007/978-1-84800-304-0_5
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