Introduction

Abstract

In traditional testing of digital complementary metal-oxide-semiconductor (CMOS) chips, emphasis is placed on functional verification and fault modeling. Push to higher frequencies has led to optimization of circuit properties and chip operating conditions for power/performance and yield. As silicon technology approaches scaling limits, there is a trend towards reducing circuit design margins and product guard-bands to squeeze maximum benefits from higher circuit densities. Such factors have been continually increasing the burden on manufacturing test. Some of these additional test challenges are addressed by examining the underlying physical behaviors and linking silicon technology, circuit design and electrical tests through models and simulations. In this chapter an overview of CMOS test, in conjunction with circuit design methodology and silicon technology performance, is provided as an introduction to the material covered in this book.