Abstract
Achieving maximum operating speed is associated with selecting geometric configurations and, what is a major consideration, with reducing the dimensions of the transistors. The main geometric parameters that are subject to minimization are the dimensions of the transistors’ active regions. These are determined by the distances between electrodes and by the size of the emitter in a bipolar transistor and the gate in a field-effect transistor. With planar devices there are techniques for obtaining horizontal (on the plane of the semiconductor wafer) and vertical structures that differ in principle. The physical processes that govern transistor operation are also quite different in the vertical and horizontal planes. We will therefore examine horizontal (Sec. 2.1) and vertical (Sec. 2.2) device configurations separately.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
P. M. Solomon, “A comparison of semiconductor devices for high-speed logic,” Proc. IEEE, 70, No. 5, 489–509 (1982).
V. Miller and H. L. Stover, “Submicron optical lithography: 1-line wafer stepper and photoresist technology,” Sol. St. Tech., 28, No. 1, 127–131 (1985).
Yu. V. Gulyaev, V. B. Sandomirskii, A. A. Sukhanov, et al., “Physical limitation on the minimum dimensions of modern microelectronic components,” UFN, 144, No. 3, 475–495 (1984).
J. T. Wallmark, “Fundamental physical limits to large-scale integration,” in: Proc. 13th Int. Conf. Phys. Semicond., Rome (1976), p. 90.
A. Sugita, M. Morita, and T. Tamamura, “Nanometer E-beam lithography using a 2-layer resist system composed on a silicon-based negative resist,” in: Extended Abstracts of the 16th (1984 International) Conference on Solid-State Devices and Materials, Kobe (Japan) (1984), p. 19.
Ch. V. Kopetskii, “Some modern trends in technology development,” Vestn. AN SSSR, No. 1, 50-64 (1985).
S. S. Yanushonis and V.-K. Yu. Yanushonene, Self-Formation in Semiconductor Technology [in Russian], Mokslas, Vilnius (1985).
C.L. Cheng, L. A. Coldren, B. I. Miller, et al., “A new self-aligned recessed-gate InP MESFET,” IEEE Trans. Electron Dev., ED-31, No. 6, 840–841 (1984).
T. Sugano, “Physical and technological limits in size of semiconductor devices,” Jpn. J. Appl. Phys., 15, suppl. 15-1, 329–330 (1976).
M. T. Elliot, M. R. Splinter, A. B. Jones, et al., “Size effects in e-beam fabricated MOS devices,” IEEE Trans. Electron. Dev., ED-26, No. 4, 469–475 (1979).
O. Ryuzan and T. Misugi, “New developments in III-V transistor technology,” Physica, 117B and 118B, 50–54 (1983).
A. C. M. Wang and S. Kakihana, “Leakage and h FE degradation in microwave bipolar transistors,” IEEE Trans. ElectronDev., ED-21, No. 11, 667–674 (1974).
A. Reisman, “Device, circuit, and technology scaling to micron and submicron dimensions,” Proc. IEEE, 71, No. 5, 550–565 (1983).
W. R. Wisseman, H. M. Macksey, G. E. Brehm, et al., “GaAs microwave devices and circuits with submicron electron-beam features,” Proc. IEEE, 71, No. 5, 667–675 (1983).
I. M. Vikulin and V. I. Stafeev, The Physics of Semiconductor Devices [in Russian], Sovetskoe Radio, Moscow (1980).
S. M. Sze, The Physics of Semiconductor Devices, 2nd Ed., Wiley-Interscience, New York (1981).
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1993 Springer Science+Business Media New York
About this chapter
Cite this chapter
Požela, J. (1993). Technological and Physical Limitations on Transistor Miniaturization. In: Physics of High-Speed Transistors. Microdevices. Springer, Boston, MA. https://doi.org/10.1007/978-1-4899-1242-8_2
Download citation
DOI: https://doi.org/10.1007/978-1-4899-1242-8_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4899-1244-2
Online ISBN: 978-1-4899-1242-8
eBook Packages: Springer Book Archive