Abstract
The wafer scale 2D array ELSA (European Large SIMD Array) is recalled in this paper. Special attention is given to recent layout results and to experiments in the reconfiguration strategy.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
G.H. Barnes et al, “The ILLIAC IV Computer,” IEEE Trans, on Computers, C-17(8), pp 746–757, Aug. 1968.
S.F. Reddaway, “DAP-A distributed array processor”, in Proc. 1st annu. symp. comput. Arch., Florida, dec. 1973, pp. 61-65.
K.E. Batcher, “Design of a Massively Parallel Processor,” IEEE Trans, on Computers, C-29(9), pp 836–840, May 1980.
D. Fusell and P. Varman. “Fault-tolerant wafer-scale architectures for VLSI”. Proceeding of the 9th annual IEEE/ACM Symposium on Computer Architecture, April 1982, pp.190-198.
K. Hedlung and L. Snyder. “Wafer-scale integration of configurable, higly parallel (CHIP) processors”. Proceeding of the IEEE International Conference on parallel Processing, 1982, pp.262.264.
F.R.K Chung, F.T. Leighton, and A.L. Rosenberg. “Diogenes: a methodology for designing fault-tolerant VLSI processor arrays”. Proceeding of the IEEE Symposium on fault-tolerant Computing, June 1983, pp.26-31.
G.J. William. “Configuration of VLSI Arrays in the Presence of Defects”. Ph. D dissertation. Stanford University. December 1983.
G. Chevalier, G. Saucier. “A programmable switch for fault tolerant wafer scale integration of processor arrays”. International Workshop On Wafer-Scale Integration, 1985. Southampton, UK.
R.A. Evans, J.V.M. Mc Canny, K.W. Wood. “Wafer Scale Integration based on Self Organization”. Int. Workshop on WSI, Southampton, 1985.
F.T Leighton and C.E Leiserson. “Wafer-scale integration of systolic arrays”. IEEE Transactions on computers, vol. c-34, No.5, May 1985, pp.448–461.
R. Negrini, R. Stefanelli. “Algorithms for Self Reconfiguration of Wafer Scale Regular Arrays”. Proc. of Int. Conference on Circuits and Sytems, IEEE, Beijing 1985.
M. Sami and R. Stefanelli. “Fault tolerance approaches for VLSI/WSI arrays”. Proc IEEE Pheonix Conf. on Comp and Comm; 1985, pp.460-468.
T. Leighton, C.E. Leiserson. “A Survey of Algorithms for Integrating Wafer Scale Systolic Systolic Arrays”. Saucier & Trihle, eds., North Holland, 1986.
Manolis G.H. Katevenis and Miriam G. Blatt, “Switch Design for Soft-Configurable WSI System”, Proc. IFIP Workshop on WSI, p. 255-270, G. Saucier and J. Trilhe, Editors, 1986.
R. Negrini and R. Stefanelli. “Comparative evaluation of space and time redundancy approaches for WSI processing arrays”. IFIP Workshop on Wafer-scale integration, Grenoble, 1986.
G. Saucier and J. Trilhe, Editors, Proc. IFIP Workshop on WSI, Grenoble, 1986.
F. Lombardi, R. Negrini, M.G. Sami, R. Stefanelli. “Reconfiguration of VLSI Arrays: A Covering Approach”. Proceedings of the 17th FTCS conference. pp. 251-256. Pittsburgh, July 1987.
E.L. Cloud, “The Geometric Arithmetic Parallel Processor,” Proc. of the Second Symposium on the Frontiers of Massively Parallel Processing, Fairfax VA, Oct. 1988.
G. Saucier, J Patry, E.F.M Kouka. “Defect Tolerance in a Wafer Scale Array for Image Processing”. International Workshop on Defect and Fault Tolerance in VLSI systems. Massasuchett, October 1988.
I. Koren, C. Stapper. “ Yield models for defect tolerant vlsi circuits: a review”. Computer systems, February 89.
G. Saucier, J Patry, E-F Kouka, “A Reconfigurable Wafer Scale Array for Image Processing”. Proc. International Conference on Wafer Scale Integration, San Francisco, US, p.277-288.
G. Saucier, J Patry “Design of an universal switching network for reconfigurable 2D-arrays”. Proc. 3rd IFIP Workshop on Wafer Scale Integration. Como, Italy, June 6–8, 1989.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1990 Springer Science+Business Media New York
About this chapter
Cite this chapter
Saucier, G., Patry, J.L., Boubekeur, A., Sanlaville, E. (1990). Practical Experiences in the Design of a Wafer Scale 2-D Array. In: Stapper, C.H., Jain, V.K., Saucier, G. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-9957-6_6
Download citation
DOI: https://doi.org/10.1007/978-1-4757-9957-6_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-9959-0
Online ISBN: 978-1-4757-9957-6
eBook Packages: Springer Book Archive