Abstract
This work examines the effect on yield, of the clustering and radial variation of fatal defects. An expression is developed for fatal defects as a function of chip area and distance of the chip from the edge of the wafer, and used to estimate the yield of successively larger numbers of array segments of a bipolar SRAM.
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References
J.E. Price, “A New Look at Integrated Circuits”, Proceedings of the IEEE, August 1970, pp. 1290-1291.
J. Shier, “A Statistical Model for Integrated-Circuit Yield with Clustered Flaws”, IEEE Transactions on Electron Devices, vol. 35, (4) April 1988, pp. 524–525.
A.J. Dingwall, “High-Yield Processed Bipolar LSI Arrays”, 1968 IEEE International Electron Device Meeting Technical Digest, p. 82.
J. Sredni, “Use of Power Transformations to Model the Yield of ICs as a Function of Active Circuit Area”, 1975 IEEE International Electron Device Meeting Technical Digest, pp. 123-125.
T. Okabe, M. Nagata, and S. Shimada, “Analysis on Yield of Integrated Circuits and a New Expression for the Yield”, Elec. Eng. Japan, vol. 92, no. 6, December 1972, pp. 135–141.
H. Murrmann and D. Kranzer, “Yield Modeling of Integrated Circuits”, Siemens Forschungs und Entwicklungs Berichte, vol. 9, no. 1, February 1980, pp. 38–40.
J. Von Bank, “An Alternative Integrated Circuit Yield Model”, IEEE Transactions on Reliability, vol. R-35, no. 4, October 1986, pp. 385–390.
T. Yanagawa, “Yield Degradation of Integrated Circuits due to Spot Defects”, IEEE Transactions on Electronic Devices, vol. ED-19, no. 2, 1972, pp. 190–197.
W.E. Ham, “Yield-Area Analysis: Part I — A Diagnostic Tool for Fundamental Integrated-Circuit Process Problems”, RCA Review, vol. 39, June 1978, pp. 231–249.
C.L. Mallory, D.S. Perlofr, T.F. Hasan and R.M. Stanley, “Spatial Yield Analysis in Integrated Circuit Manufacturing”, Solid State Technology, vol. 26, no. 11, November 1983, pp. 121–127.
A.V. Ferris-Prabhu, “Defects, Faults and Semiconductor Yield”, International Workshop on Defect and Fault Tolerance in VLSI Systems, Paper 1.1, Springfield, Mass., October 3–5, 1988.
A.V. Ferris-Prabhu, L.D. Smith, H. Bongcs and J.K. Paulsen, “Radial Yield Variations in Semiconductor Wafers”, IEEE Circuits and Devices Magazine, vol. 3, no. 2, March 1987, pp. 42–47.
A. Gupta and J. Lathrop, “Yield Analysis for Large Integrated-Circuit Chips”, IEEE J. Solid State Circuits, vol. SC-7, no. 5, October 1978, pp. 389–395.
D.M.H. Walker, Yield Simulation for Integrated Circuits, Kluwer Academic Publishers, 1987, p.158.
A.V. Ferris-Prabhu, “A Cluster-Modified Poisson Model for Estimating Defect Density and Yield”, IBM Technical Report, TR19.90425, March 1989.
A.V. Ferris-Prabhu and N.D. Lubart, “Reliability Analysis for Simple Systems”, Microelectronics and Reliability, vol. 15, 1976, pp. 555–560.
D.M.H. Walker and S.W. Director, “VLASIC: A Yield Simulator for Integrated Circuits”, IEEE International Conference on Computer-Aided Design, Digest of Technical of Technical Papers, November 1985, pp. 318-320.
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Ferris-Prabhu, A.V., Retersdorf, M.A. (1990). The Effect on Yield of Clustering and Radial Variations in Defect Density. In: Stapper, C.H., Jain, V.K., Saucier, G. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-9957-6_5
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