Abstract
Architectures for analog-to-digital (A/D) conversion above 100 Msamples-per-second are described. The well known pipeline and flash configurations are examined, including variations which reduce complexity and power consumption. Static and dynamic errors common to flash architecture A/D circuits are enumerated. The advantages of sample and hold (S/H) circuits in reducing dynamic errors in flash converters are described. A simple model for sample and hold circuits is used to predict S/H performance limits and sources of error.
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References
Yukio Akazawa, et al., “A 400 MSPS 8b Flash AD Conversion LSI”, ISSCC Digest of Technical Papers, 1987, pp. 98–99
Bruce Peetz, et al., “An 8-bit 250 Megasample per Second Analog-to-Digital Converter: Operation Without a Sample and Hold”, IEEE Journal of Solid-State Circuits, vol. SC-21, no. 6, December 1986, pp. 997–1002
Yuji Gendai, et al., “An 8b 500MHz ADC”, ISSCC Digest of Technical Papers, 1991, pp. 172–173
Ken Poulton, Hewlett-Packard Laboratories, private communication
Robert A. Blauschild, “An 8b 5Ons Monolithic A/D Converter with Internal S/H”, ISSCC Digest of Technical Papers, 1983, pp. 178–179
Robert Jewett, et al., “A 12b 20MS/s Ripple-through ADC”, ISSCC Digest of Technical Papers, 1992, pp. 34–35
Stephen H. Lewis, et al., “A Pipelined 5 MHz 9b ADC”, ISSCC Digest of Technical Papers, 1987, pp. 210–211
David Robertson, et al., “A Wideband 10-bit, 20 MSPS Pipelined ADC using Current-Mode Signals”, ISSCC Digest of Technical Papers, 1990, pp. 160–161
John J. Corcoran, et al., “A 400MHz 6b ADC”, ISSCC Digest of Technical Papers, 1984, pp. 294–295
T.W. Henry, et al., “Direct Flash Analog-to-Digital Converter and Method”, U.S. Patent 4, 386, 339
Adrian P. Brokaw, “Parallel Analog-to-Digital Converter”, U.S. Patent 4, 270, 118
Rob E.J. van de Grift, et al., “An 8b 50 MHz Video ADC with Folding and Interpolation Techniques”, ISSCC Digest of Technical Papers, 1987, pp. 94–95
Rudy van de Plassche, et al., “An 8b 100 MHz Folding ADC”, ISSCC Digest of Technical Papers, 1987, pp. 94–95
Johan van Valburg, et al., “An 8b 650 MHz Folding ADC”, ISSCC Digest of Technical Papers, 1992, pp. 30–31
Yoji Yoshii, et al., “An 8b 350 MHz Flash ADC”, ISSCC Digest of Technical Papers, 1987, pp. 96–97
V.E. Garuts, et al., “A Dual 4-bit, 1.5 Gs/s Analog-to-Digital Converter”, 1988 Bipolar Circuits and Technology Meeting Proceedings, pp.141–144
Ken Rush, et al., “A 4 GHz 8b Data Acquisition System”, ISSCC Digest of Technical Papers, 1991, pp. 176–177
Ken Poulton, et al., “A 1-GHz 6-bit ADC System”, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, December 1987
S. Prasad, et al., “An Implant-Free 45 GHz A1GaAs/GaAs HBT IC Technology Incorporating 1.4 THz Schottky Diodes”, 1991 Bipolar Circuits and Technology Meeting Proceedings, pp.79–82
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© 1993 Springer Science+Business Media Dordrecht
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Corcoran, J. (1993). High Speed Sample and Hold and Analog-to-Digital Converter Circuits. In: Huijsing, J.H., van der Plassche, R.J., Sansen, W. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2233-8_7
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DOI: https://doi.org/10.1007/978-1-4757-2233-8_7
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