The CMOS Gain-Boosting Technique

Abstract

The Gain-Boosting Technique improves accuracy of cascoded CMOS circuits without any speed penalty. This is achieved by increasing the effect of the cascode transistor by means of an additional gain-stage, thus increasing the output impedance of the sub-circuit. Used in opamp design, this technique allows the combination of the high-frequency behaviour of a single-stage opamp with the high DC-gain of a multi-stage design. Bode-plot measurements show a DC-gain of 90 dB and a unity-gain frequency of 116 MHz (16 pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behaviour corresponding with a closed loop bandwidth of 18 MHz (35 pF load) and a settling accuracy better than 0.03 percent. A more general use of this technique is presented in the form of a transistor-like building block: the Super-MOST. This compound circuit behaves as a normal MOS-transistor but has an intrinsic gain g _m · r ₀ of more than 90 dB. The building block is self biasing and therefore very easy to design with. An opamp consisting of only 8 Super-MOSTs and 4 normal MOSTs has been measured showing results equivalent to the design mentioned above.