Design Techniques for a Self-Checking Self-Exercising Processor

Abstract

Dormant faults and latent errors can impair recovery of fault tolerant systems. For some, a relatively long time may occur before detection. This can jeopardize recovery because hardware faults or transient errors can accumulate. Since most fault recovery mechanisms are only designed to cope with a single fault, accumulated faults during the recovery process may cause system failure. Several studies have shown that latent faults cannot be ignored in highly reliable systems [ShMc 75], [ShMc 76], [Chil 86], [Shin 86] and [Swer 87]. This is especially a problem in some aerospace systems which must operate in very severe environments in which high rates of transient errors are expected and external disturbances may cause multiple faults. This paper investigates VLSI design techniques which can search for these latent faults actively to allow rapid recovery before multiple errors build up. The basic principle of these techniques is to implement a system with concurrent error detection. Very short test cycles are then inserted into the system periodically as it performs its normal program execution in order to expose and detect latent errors and faults. The rate of inserting these test cycles is chosen (typically every 100 execution cycles) such that the entire system can be exercised in a fraction of a second. The goal is to achieve self-exercising without an excessive hardware overhead (beyond the initial design for concurrent fault-detection which is needed for fault-tolerance anyway) or significantly degrading the system performance. These techniques are also used to provide rapid hardware diagnosis, to simplify initial testing, (a major expense in space programs) and to provide the possibility of on- line acceptance testing (i.e. testing a circuit by just running applications programs.) A previous paper described how self-checking, self-exercising design could be effectively employed in memory [Renn 86]. This paper extends the approach to the processor.