Abstract
Clock distribution is critical for determining system performance and power dissipation. In this chapter, several issues involved in low power clock distribution have been addressed. To minimize the power dissipated by clock, thedistributed buffering schemeshould be used instead of thesingle driver schemebecause of its advantages in reducing wiring capacitance and driver power dissipation. In using thedistributed buffering scheine, the process variation induced skews should be taken into account and an optimization method can be used to remedy this problem. For low power systems, tolerable skew instead of zero-skew should be considered as the goal of clock distribution to relax the delay balance constraints and reduce total capacitance. We can also apply a two-level clock distribution scheme by taking advantage of the flip-chip packaging and area-pad technology. By placing the global level clock tree on to the package level and lock clock trees on the chip, the clock delay and power can be substantially reduced in either a single-chip or an MCM system. Moreover, low-voltage differential driver and receiver circuits can be designed when using the flip-chip packaging technology to further reduce loading capacitance and power dissipation.
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Xi, J.G., Dai, W.WM. (1996). Low Power Clock Distribution. In: Rabaey, J.M., Pedram, M. (eds) Low Power Design Methodologies. The Springer International Series in Engineering and Computer Science, vol 336. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2307-9_5
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DOI: https://doi.org/10.1007/978-1-4615-2307-9_5
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