Power Transmission and Voltage Regulation

Abstract

Issues related to the voltage regulation in remotely powered implants are discussed in this chapter. Two on-chip low drop out (LDO) voltage regulators are presented which target two different specification sets, and which are incorporated into two versions of the Neuro+ IC. The first LDO voltage regulator is proposed to support the Neuro+I and provides 1.8 V output voltage. The regulator is stable over the full range of alternating load current and provides fast load regulation, which is achieved by applying a time -domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024 %, and a PSRR of 37 dB at a 1 MHz power carrier frequency . The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6 $\upmu$s, at full load transition. The total ground current including the bandgap reference circuit is $28\,\upmu$A and the active chip area measures 0.104 mm$^{2}$ in a $0.18\,\upmu$m CMOS technology. The second LDO voltage regulator targets the Neuro+II and generates a 1.2 V output voltage. The regulator is stable over the full range of the load current up to 20 mA and supports burst mode of operation using a robust start-up circuit in the bandgap reference circuit. The Regulator achieves a line and load regulation of 3.45 % and 0.11 V/A, respectively. The sample prototype occupies a silicon area of 0.073 mm$^{2}$ in a $0.18\,\upmu$m CMOS technology.