Abstract
In this chapter the implementation of a two-stage latch PUF including preselection circuitry is introduced. The preselection circuit includes a binary weighted biasing block that allows for considerable error rate reduction. The implementation details and measurement results are presented. The effect of preselection is analyzed in more detail. The implementation was carried out in a 90 nm technology.
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References
Hofer M, Boehm C (2010) An alternative to error correction for sram-like pufs. In: CHES – workshop on cryptographic hardware and embedded systems, pp 335–350
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© 2013 Springer Science+Business Media New York
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Böhm, C., Hofer, M. (2013). PUF with Preselection. In: Physical Unclonable Functions in Theory and Practice. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-5040-5_14
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DOI: https://doi.org/10.1007/978-1-4614-5040-5_14
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-5039-9
Online ISBN: 978-1-4614-5040-5
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